Do Alternative Memories Need to Meet the 3-Nanometer Test?

Can memories with features below three nanometers be mass produced?

2 min read
Do Alternative Memories Need to Meet the 3-Nanometer Test?

Last month, an article in the pages of IEEE Spectrum looked at how alternative memories were getting the so-called carbon nanotube test.

The article describes the work of Stanford researchers, led by H.-S. Philip Wong, in testing the capabilities of two different types of alternative memory to flash, namely resistive random-access memory (RRAM) and phase-change memory (PCM). I myself have covered in this blog Eric Pop's research into PCM.

But in the recent past, those alternative memories that have taken on flash, such as IBM's much ballyhooed Millipede Project, have suffered ignominious ends. 

We are told, however, that flash memory cannot rule the roost forever because of density limits. So alternatives must be found.

With the pressure on, up step RRAM and PCM. And in the article we learn that some companies are planning to introduce PCM and RRAM memories in the near future. With commercial introduction possible so soon, Wong thought it might be worthwhile to see how far the technology can scale. So they went right to the limit, using 1.2-nanometer-wide nanotubes as electrodes.

Ultimately, Wong and his team were able to produce an RRAM cell measuring 6 by 6 nm that was fully operational. Since the memory cell switches with less than 10 microamperes of current and about 10 volts, which meets expectations derived from previous experiments, it serves as a sign that RRAM will scale well, according to Wong.

But while I was reading this I couldn’t help but think about the paper recently presented by Professor Mike Kelly at Cambridge University that claims that structures with dimensions of 3 nm or less cannot be mass-produced. 

Now, drawing a line in the sand of technological progress is a risky—and rarely rewarding—exercise. But Kelly would seem to have presented some pretty plausible reasons for why he drew that line.

I wonder how seriously the companies that are nearing the introduction of some kind of PCM or RRAM products in the coming years are considering this theoretical threshold. Maybe a 3-nm test should be instituted.

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Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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