10 November 2010—Taiwanese researchers say they have invented the smallest nonvolatile resistive RAM (RRAM) architecture yet. RRAM stores bits as a change in the resistance of a memory cell. Big chip firms are intensively investigating RRAM, and the Taiwanese government finds the technology particularly compelling because it might help to reinvigorate the country’s memory industry, which is gradually declining and desperately in need of new technology.
The memory owes its small footprint to its use of a new type of bipolar junction transistor, or BJT, rather than a conventional metal-oxide semiconductor field-effect transistor, or MOSFET. The BJT, which is vertically oriented, drives current through the memory cell to either read a bit or, by changing the cell’s resistance, to write one. In the Taiwanese design, the cell—a film of titanium nitride, titanium, and hafnium oxide sandwiched between two conductors—sits atop the transistor. In previous designs using MOSFETs, the driving transistors were on the sides of the memory cells.
According to Chrong Jung Lin, who heads the Microelectronics Lab in the department of electrical engineering at National Tsing Hua University, dozens of his teammates have spent two years designing the unique BJT that makes a 3-D RRAM cell possible. Engineers at the Industrial Technology Research Institute (ITRI), a quasi-governmental research and development organization, were also involved in the work.
Together they fabricated an array of 3-D RRAM cells that each took up 0.032 square micrometer (using 90-nanometer CMOS logic technology), or four times the square of the smallest feature in the chip (4F2 in industry parlance).
"The advantages of the high-density three-dimensional RRAM cell include low voltage operation, better reliability, and superior scalability," says Lin. He says that such an area-saving memory can compete with or even replace flash memory.
Lin’s team will report details of its invention at the upcoming IEEE International Electron Devices Meeting, which will be held in San Francisco in early December.
According to Lin, forming the BJT beneath the cells was key. "It’s like placing required stuff in the basement of a single-story house rather than [in] extended adjacent areas. You don’t have to use extra land," he says.
The choice of a BJT also means that the new RRAM cell is entirely decoupled from the size of the CMOS logic transistor structures, such as the gate length and oxide thickness. As a result, the cell layout can be more easily arranged and scaled down to 4F2.
Lin adds that the new RRAM cell consumes less power, because the BJT can be efficiently operated at a low 2 volts to erase a bit and at 1.5 V to write one. In contrast, the lowest external applied voltage to operate a flash memory cell is nearly 10 V, he says.
In terms of reliability, the new RRAM can sustain more than 10 million write/erase cycles without significant degradation. The minimum acceptable for flash is 10 000 cycles.
The team took pains to make a memory that was compatible with the CMOS process, which is the manufacturing scheme for silicon logic chips. Because of that, the cell can be made smaller as engineers make logic circuits smaller. Lin’s team is working with a Taiwanese foundry, which he would not name, to demonstrate the technology’s large-scale manufacturability.
The Taiwanese government is considering investing millions of dollars in the BJT RRAM, according to Lin. If this funding is approved, a multiple-year intensive research project, jointly proposed by ITRI and Lin’s team at the university, would be launched in 2011, he says.