Band-Gap Engineering of Nanowires Could Boost Batteries

Energy barriers could keep nanowire electrodes from cracking in lithium-ion batteries and increase energy density

2 min read
Band-Gap Engineering of Nanowires Could Boost Batteries

The reason for replacing graphite in the electrodes of the ubiquitous lithium-ion (Li-ion) battery is clear to anyone who uses a smartphone: The batteries run out of charge in just a few hours under regular use.

One answer has been to replace the graphite with silicon. Unfortunately, the expanding and contracting that occurred as the lithium ions transported in and out of silicon electrodes quickly cracks it.

The next solution was to create “nanostructured silicon” electrodes, sometimes with the help of graphene or good old carbon nanotubes.

Now researchers at the University of California San Diego (UCSD) have brought a new perspective to the issue. They are  taking a page from band-gap engineering, in which heterostructures are used to create energy barriers between electrons and holes, and applied the concept to creating barriers to the ions as they enter into an electrode so they diffuse in a very specific way.

The research, which was published in the journal Nano Letters (“Tailoring Lithiation Behavior by Interface and Bandgap Engineering at the Nanoscale”), describes a method by which the typical surface diffusion of lithium ions into a nanowire electrode is blocked and instead the ions are diffused layer-by-layer along the length of the nanowire.

As the Nano Letters article notes: “These results demonstrate for the first time that interface and band-gap engineering of electrochemical reactions can be utilized to control the nanoscale ionic transport / insertion paths and thus may be a new tool to define the electrochemical reactions in Li-ion batteries.” 

In the video below you can see the different way this impacts the nanowire. Instead of blowing up around its middle, it gradually grows along its axis as the lithium ions transport into the nanowire. The video also demonstrates some new breakthroughs in nanoscale imaging with transmission electron microscopy. It shows lithium-ion reactions in real time at nanoscale precision.

In the press release about his work, Shadi Dayeh, a professor at UCSD, explains that this control of how the ions diffuse could result in “an effective way to tailor volume expansion of lithium ion battery electrodes, which could potentially minimize their cracking, improve their durability, and perhaps influence how one could think about different electrode architectures.”

The new technology starts with germanium nanowires that are then coated with silicon.The research builds on previous work of Dayeh and his colleagues published in the journal Applied Physics Letters and again in Nano Letters in which they demonstrated control over the heterostructuring of germanium-silicon nanowires.

 According to Dayeh, the new electrodes would allow for battery designs in which the expansion of the electrodes would not cause any shorting between the cathode and the anode.

Images: UC San Diego Electrical and Computer Engineering

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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