GlobalFoundries CTO on Why the Company Abandoned the “Bleeding Edge”

“This was the right decision,” says Gary Patton

Global Foundries CTO Gary Patton
Photo: Global Foundries

Earlier this week, GlobalFoundries announced that it was halting development of its 7-nanometer manufacturing technology, effectively ending its climb toward the limits of Moore’s Law.

When IEEE Spectrum met the company’s CTO, Gary Patton, in October 2017, he was driving the move to the 7-nm node at the Fab 8 facility in Malta, N.Y. He was optimistic, but described the process as “an extreme sport.” That month GlobalFoundries was in the midst of installing the first of what would be two extreme ultraviolet lithography (EUV) systems, machines that would reduce the cost of 7-nm processes and enable 5- and 3-nm processes in the future.

But Patton, an IEEE Fellow, also described other technological advantages the company was striving for, such as fully depleted silicon-on-insulator (FDSOI) technology and embedded MRAM. With the end of GlobalFoundries 7-nm hopes, those will now get extra money and attention, he told IEEE Spectrum in a telephone interview Wednesday.

IEEE Spectrum: What was your advice to CEO Tom Caulfield during this decision?

Gary Patton: Clearly as a technical guy, I love the tech challenges of bleeding edge, but for our employees, for our customers, for our shareholders, at the end of the day we have to be a profitable business and a sustainably profitable business. We all stared at the numbers, and it was pretty clear that for the bleeding edge stuff, the [return on investment] is continuing to erode. I think you see in the press and you’ve probably written about it—Moore’s Law is slowing down. There are fewer customers at the leading edge. The capacity needed at the leading edge is going down with each [manufacturing process technology] node, and at the same time the R&D expense is escalating. It’s tough to get off of the R&D spending drug and sit back and actually rake in the revenue.

I see three dimensions of innovation. One was keeping Moore’s Law going with EUV, stacked nanowires, vertical FETs, and things like that.  [There are] two other dimensions of innovation that we are focused on. One was differentiated silicon: Think of that as our [fully depleted silicon-on-insulator] play, RF technology, things like integration of high voltage onto the same chips, integration of memory. And then also enabling our customers with system level integration capabilities through 2.5D and 3D packaging, through silicon photonics, and through embedded memory.

We’re really going to focus on those two dimensions of innovation, and as we look at it, that offers our best avenue for profitability and for a return on our investment. If we can be profitable and we can get a good return on investment, that’s good for our employees, our shareholders, and good for our customers for us to be viable long term. As a technology guy it’s a hard decision, but I supported it. I looked at the numbers and I couldn't argue with them. This was the right decision.

IEEE Spectrum: So you’re increasing funding in those areas, not just eliminating the advanced manufacturing node spending?

Gary Patton: There’s absolutely an increase in the R&D for these other areas. Now that we’re relieved from the burden of having to fund this bleeding edge stuff, we’re able to redirect dollars and resources toward these other areas…. We did do a resource action and we are cutting back our development corps here in Malta. But doing differentiated strategy around 14-nm and 12-nm, it requires some significant resources, and we’ve moved people over to that. But it’s nowhere near the scale of this crazy bleeding edge stuff of 7-nm and beyond.

IEEE Spectrum: What are you going to do with the two EUV machines you installed?

Gary Patton: We’ll be working with ASML to figure out the best use of them. A likely or possible outcome is that we end up selling those tools.

IEEE Spectrum: How much room for improvement is there at 14/12-nm?

Gary Patton: I don’t think I can quote an exact number at this point, but I definitely believe there’s a lot of innovations we did as part of the 7-nm work that we’ve already pulled into our 14/12 program. And there’s further enhancements that we’ll be pulling in. But that’s only one thrust. The other thrust is integration of RF, integration of embedded memory, eventually integration of things like high-voltage capability. We’ve got a pretty active activity right now in 14/12-nm around 2.5 and 3D integration, and we’ll be doubling down on that.

IEEE Spectrum: Will this be enough to distinguish GlobalFoundries from its competition?

Gary Patton: Absolutely. I think you know we’re a leader in RF space; we have the largest market share. We’re leading in FDSOI and crossed the $2 billion mark for design wins. That leverages these things that I just talked about, things like integrating RF on the same chip for 5G and millimeter wave. We think with our portfolio we’re well positioned for a number of high-growth areas like 5G, IoT, AI—at the edge especially, AR/VR.

IEEE Spectrum: The integration of high-voltage systems onto chips is new to a lot of people. Can you share a road map of that development?

Gary Patton: Not yet. Hopefully we’ll have updates at our Design & Technology Conference at the end of September in Santa Clara. We do have an extensive high-voltage portfolio, that’s a major focus in Singapore, and because of the demand we’ve shifted some manufacturing to Dresden as an added source for that high-voltage technology.

IEEE Spectrum: Your next step in fully depleted silicon-on-insulator technology is a 12-nm technology called 12FX. At one point it seemed like it would perform as a competitor to 7-nm technology. Is that still the case?

Gary Patton: I don’t think it really competes. We got a little confused ourselves last year, to be honest, regarding competition with 7 nm. Really, it’s a different marketplace. It’s really about customers who decided to go the FDSOI path who are looking for that blend of power, performance, and cost with integration of RF capability, for example. They need to take those products that they’re [working with us on] today at 22-nm FDSOI. And at the right time, probably three years from now, [they’ll] be able to [send us designs for] a product at 12 nm.

IEEE Spectrum: Will customers who aren’t already at 22-nm FDSOI have reason to jump in?

Gary Patton: Everybody gets excited about leading edge. But if you look at the statistics and even out at 2022, about 75 percent of the market is at nodes of 12 nm and over. And two-thirds of the market hasn’t made the jump into [either SOI or FinFET] and are operating on older technology nodes. So we see tremendous opportunity for growth in our FD platform.

The Semiconductors Newsletter

Monthly newsletter about how new materials, designs, and processes drive the chip industry.

About the Nanoclast blog

IEEE Spectrum’s nanotechnology blog, featuring news and analysis about the development, applications, and future of science and technology at the nanoscale.