Getting EUV Ready for 2020

Fixes to chemistry and design needed to extend lithography cost savings, according to Imec analysis

EUV single patterning of the N5 32-nm metal-2 layer, 32-nm pitch dense lines, and 40-nm hexagonal contact holes and pillars
Image: Imec
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Extreme-ultraviolet lithography looks ready for its debut later this year, making it easier to build huge numbers of chips with even more huge numbers of the tiniest circuits you can buy. But will EUV be ready for the next generation, when circuits are slated to be even tinier? The Belgian microelectronics research house Imec has uncovered some problems with using EUV for the so-called 5-nanometer generation, which is expected to go into full production in late 2020. They are fixable, says Kurt Ronse, program director on advanced patterning at Imec, but there’s quite a lot of work to be done.

EUV uses light with a wavelength of 13.5-nm to define the features that become the transistors and interconnect wiring of a chip. The light is reflected off a pattern onto a photomask and cast onto a chemical coating on the silicon wafer called a photoresist. The photoresist hardens where the light strikes it, transferring the photomask’s pattern onto the silicon.

The 13.5-nm wavelength is considerably smaller than the space between interconnect lines—the 32-nm “pitch”—needed even for the 5-nanometer process. But there’s more to lithography than a slim wavelength. And when Imec engineers began producing experimental features for 5-nm chips last year, they noticed many more defects than they’d expected.

They built rows of trenches of the kind that would form a chip’s wiring once filled with metal and arrays of holes that would become the contacts from the wiring to the parts of the transistors below. But there were “nanobridges” between the trenches, holes that were missing, and holes that had merged with their neighbors, Ronse says. Such random snafus are collectively called stochastic defects.

What causes them? “That’s the million-dollar question,” says Ronse. They can be caused by what’s called photon shot noise. It’s the fact that there are few photons falling on the chip and you just don’t always get the same number at every spot on the chip. “But we started to analyze defects more in detail, and we saw way too many to be explained all through photonic shot noise,” he says.

Simply cranking up the number of photons by exposing an area longer would help, but not enough, he says. Besides, longer exposure means a slower manufacturing process. And nobody wants that.

Another culprit is likely a sort of chemical version of shot noise. The photoactive chemicals in the photoresist may not be perfectly uniformly distributed on the wafer, leaving spots that act as though they are underexposed. And Ronse says there are interactions with the layers beneath the photoresist.

Optimization of all these aspects, as well as layout changes for the metal interconnect layers of logic circuits, should result in a 5-nm processes ready for a 2019 debut, Ronse says. Imec reported its findings at the SPIE Advanced Lithography Conference held this week in San Jose, Calif.

This post was corrected on 1 March 2018.

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