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Low-Power AI Startup Eta Compute Delivers First Commercial Chips

The firm pivoted away from riskier spiking neural networks using a new power management scheme

3 min read
A computer chip with graphs next to it
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When Eta Compute began, it was among the few adherents of spiking neural networks (SNNs) as the low-power path to AI for small and battery-power-constrained sensors and gadgets. But even as the startup was showing off its successes at this, it was realizing SNNs were not ready for prime time.

Using an unrelated technology the company had in development, Eta Compute pivoted toward more traditional neural networks such as deep learning and is reaping the rewards. The West Lake Village, Calif.-based company revealed on Wednesday that its first production chips using that technology are now shipping.

“We've got a number of customers lined up working on a number of different projects,” says CEO Ted Tewksbury. “These customers have just been waiting for the production silicon and as soon as we get it in their hands, we are confident that we're going to start to sell.”

The chip, called the ECM 3532, consumes as little as 100 microwatts and is designed to perform AI-enabled tasks such as object identification, recognize wake words or sounds, and analyze data from a variety of sensors. Eta Compute’s technology “is orders of magnitude more power-efficient than any other technology I have seen to date, and it will certainly make AI at the edge a reality,” said Jim Feldhan, president and founder at Semico Research in a press release.

The chip is emblematic of a drive to provide AI to “edge” devices, such as battery-powered cameras, microphones, and other IoT sensors. Part of the attraction is that battery power can be saved by not having to transmit a continuous stream of data to the cloud. For example, a smart building control system could use a low-power, low-resolution camera to determine if a room is occupied. Rather than send a raw stream of video to an off-site computer, AI embedded in the camera could simply report the number of people it detects.

The ECM 3532 is a system-on-chip built around an Arm Cortex-M3 processor core and an NXP CoolFlux DSP core. But the key is an in-house technology called continuous voltage and frequency scaling, or CVFS. CVFS allows the system to throttle the voltage and frequency of each core independently. Lowering the operating voltage of a circuit and the frequency at which it operates saves power—however, it slows computation as well. But because sensor data tends to be episodic or “lumpy”, most of the time the ECM 3532 can run at low voltage and low frequency. For example, an alarm system microphone waiting to hear the sound of braking glass would have the ECM 3532 running at low voltage and low frequencies most of the time.

CVFS might sound similar to a microprocessor technology called dynamic voltage and frequency scaling (DVFS), but there are key differences, explains Tewksbury. DVFS allows only a set of discrete voltages and frequencies. But in CVFS voltage and frequency can range over a continuum. An algorithm constantly examines the cores’ incoming workloads and determines the voltage and frequency they require to handle the work using a minimum of energy.

Power efficiency was part of Eta Compute’s original attraction to spiking neural networks. In a demo of Eta Compute’s TENSAI chip in 2018, the network recognized a cheetah in a video using fewer than 1,000 pixels, while a convolutional neural network needed 100,000. But even as Eta Compute was demonstrating TENSAI’s capabilities there were warning signs that it wasn’t the way to go.

For one, the asynchronous logic—where computing proceeds without a clock—needed for the spiking network took up a lot of area, which could be a problem if your target market is small, battery-driven systems. Another problem is that the network’s efficiency, while excellent at lower frequencies, dropped off above 5 megahertz. And finally, the state of spiking neural network algorithms “was nowhere near ready for prime time,” says Tewksbury.

Eta Compute made the announcement regarding ECM 3532 at the TinyML Summit, in San Jose.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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