Breakthrough in Creating a Band Gap for Graphene Promises Huge Potential for Electronic Applications

A Q&A with IBM Fellow Phaedon Avouris provides more details on this groundbreaking graphene for electronics research

3 min read
Breakthrough in Creating a Band Gap for Graphene Promises Huge Potential for Electronic Applications

Ever since graphene was first produced in a lab at the University of Manchester in 2004, researchers around the world have been fascinated with its potential in electronics applications.

Graphene possessed all the benefits of carbon nanotubes (CNTs), namely its charged-carrier mobility, but it didn’t have any of the down sides, such as CNTs’ need for different processing techniques than silicon and the intrinsic difficulty of creating interconnects for CNTs.

But all was not easy for applying graphene to electronics applications. One of the fundamental problems for graphene was its lack of a band gap, which left it with a very low on-off ratio measured at about 10 as compared to in the 100s for silicon.

Now this fundamental hurdle has been overcome. Based on research led by Phaedon Avouris at IBM’s IBM T.J. Watson Research Center, Yorktown Heights, New York, IBM is reporting that they have created a significant band gap in graphene.

The research as reported in NANO Letters relates how the researchers were able to create a band gap and a resulting large current switching on/off ratio at room temperature.

IBM researchers achieved this by using a bi-layer (two-layer) designed graphene field-effect-transistor with a polymer insulating the high-k gate dielectric from the graphene transistor channel. The results in experiments have demonstrated that 130 meV can be opened by a strong vertical electric field and an on-off current ratio of 100 is achieved at room temperature and a few thousand at lower temperatures.

Due to the great potential that this research promises for using graphene in applications including digital electronics, tunable terahertz technology, and infrared nanophotonics, IBM has given us the opportunity to do a Q&A with Phaedon Avouris, which we have below.

In addition, in the following days we will also run a Q&A with another representative of IBM research on the overall strategy in pursuing nanoelectronics, specifically with graphene and carbon nanotubes.

Answers by Phaedon Avouris, IBM Fellow and Manager, Nanometer Scale Science & Technology

With the solution that you have come up with for creating a band gap in graphene, what, if any, are the tradeoffs for graphene’s electronic properties?

Using bilayer graphene instead of monolayer would, in principle, lead to a lower intrinsic carrier mobility. However, the mobilities of both materials are so high, much above what is technologically needed, that in reality it makes no difference which one you use. In fact, technologically, bilayer has advantages because electrical noise is lower and there is an intrinsic screening of the influence of trapped charges in the gate dielectric which affect very much the mobility in the monolayer.

A number of other approaches have been identified or implemented for creating band gaps in graphene. What is better about your approach, i.e. bigger band gap, easier to produce?

The lack of band-gap in graphene is based on the fact that the unit cell of graphene has two atoms which are equivalent (have the same potential). To generate a band gap one has to make the two atomic sites have different potential. This is difficult given they are 0.15 nanometers apart. Another approach is to reduce the dimensionality of graphene from 2D to 1D, i.e. make a nanoribbon. This opens a bandgap through the 1D confinement of the electrons. However, to open a usable bandgap for digital electronic applications one needs nanoribbon widths of the order of 2nm. This is beyond the current limits of controlled fabrication techniques and the resulting edge roughness drastically reduces the mobility.

In 2006 E. McCann theoretically predicted that applying a strong vertical electric field to a graphene bilayer would open up a bandgap. This bandgap could be tuned with increasing E-field. This is, in principle, a simpler approach that we have chosen to investigate.

You have indicated that the on-off current ratio with the new graphene-based FET is around 100 at room temperature. How much do you think it will be possible to improve that ratio at room temperature through scaling down the thickness of the insulating layers?

The on/off ratio depends not only on the bandgap, but also on the carrier scattering in the graphene. We are currently working to increase the electric field working with thinner and higher k dielectrics and also to make purer graphene. The experiments would tell us what is technologically feasible. However, having a tunable bandgap in graphene of the size that we have achieved already opens up the possibility of applications in many areas such as graphene optoelectronics, e.g. IR and THz detectors and emitters.

Does your bilayer design and insulated high-k gate dielectric present itself for easy manufacturability?

Yes, it is manufacturable. However, we are still exploring even better dielectric stacks and improved device architectures.

Creating a band gap in graphene has been identified as a critical step in using the material in electronics. With the band gap issue addressed, at least with this most recent device, what major obstacles still stand in the way now for graphene in electronics applications? 

The bandgap issue has been addressed, but not fully resolved yet. We are still exploring how far we can go. In general graphene large scale fabrication has made great progress, but homogeneity issues are still present and are intensively pursued.

The Conversation (0)

3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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