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Novel Nanostructures Give Boost to Phase Change Memory

KAIST researchers reduce power consumption of PRAM, overcoming one of its shortcomings in mobile electronics

2 min read
Novel Nanostructures Give Boost to Phase Change Memory
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Flash memory is that non-volatile (NV) memory that everyone believes is ripe to be displaced in mobile electronics. But instead it has remained remarkably resilient undergoing just enough incremental improvements over the years to maintain its dominant position in the field.

Among the alternatives attempting to mount a commercial challenge to flash is phase-change random access memory (PCRAM or PRAM).  PRAM operates by heating a material in the memory cell that switches between a conductive crystalline phase and a resistive amorphous phase, imparting the binary characteristic necessary for memory.

While Samsung has commercialized PRAM with a 512Mb device, its writing current has to be reduced by at least one-third if it is to find wide adoption in mobile electronics, according to Korean Advanced Institute of Science and Technology (KAIST). Now those researchers claim to have taken a significant step towards achieving this lower power consumption by employing a new type of nanostructure for the PRAM.

The material, which is described in the journal ACS Nano ("Self-Assembled Incorporation of Modulated Block Copolymer Nanostructures in Phase-Change Memory for Switching Power Reduction"), employs self-assembled block copolymer silica nanostructures.  Block copolymers are particularly attractive in this application because they can produce self-ordered arrays with sub-20 nm features through relatively simple spin-coating and plasma treatments.

The real payoff with the new material is that it has resulted in a five-fold decrease in the required writing current, which corresponds to a power reduction of five percent.

One strategy for reducing switching power consumption in PRAM has been by decreasing the size of the contact area between the heating layer of the PRAM and the actual phase-change materials. The KAIST researchers achieved this by incorporating the silica nanostructures on top of the phase-change material.

"This is a very good example that self-assembled, bottom-up nanotechnology can actually enhance the performance of electronic devices,” says Keun-Jae Lee, one of the lead KAIST researchers, in a press release. “We also achieved a significant power reduction through a simple process that is compatible with conventional device structures and existing lithography tools."

Whether this will be the feature that can help PRAM compete with flash is not clear. But one can imagine that KAIST's national neighbor--Samsung--will be intrigued by this latest development.

Illustration: KAIST

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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