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New Sorting Process for Carbon Nanotubes Prepares Them for Flexible Electronics

An easier method for sorting nanotubes using a polymer has been developed that could help the different varieties be targeted where they can best be used

2 min read
New Sorting Process for Carbon Nanotubes Prepares Them for Flexible Electronics

Researchers attempting to use carbon nanotubes (CNTs) in electronics have faced many obstacles, but perhaps the two most fundamental problems have been: putting them where you want them to go and developing a process that promises a homogeneity of CNTs.

Researchers at the University of California Davis and Stanford University, led by Zhenan Bao, who has been using CNTs for creating pressure sensors for use in an artificial skin, along with the Samsung Advanced Institute of Technology have developed a process by which the semiconducting single-walled carbon nanotubes are separated out from a mixture.

The researchers published their work in the journal Nature Communications.

"Sorting has been a major bottleneck for carbon nanotubes to be viable for practical electronics applications," Bao said. "This work solves the problem of separating the conducting from the semiconducting nanotubes."

The problem has been the conducting variety of CNTs and the semiconducting species have quite different application areas where they excel. This separation process could mean that the semiconducting CNTs can be sorted out and used for transistors and the conducting nanotubes can be used for wires and electrodes.

The method the researchers developed for carrying out this separation involves a polymer that wraps itself around the semiconduting and non-conducting CNTs. While researchers have developed polymers in the past that accomplish this, the problem with those polymers was that they insulated the CNTs and required extensive removal treatments to get the polymer off the CNTs.

This polymer does not need to be removed since it can be used as is as a semiconducting nanotube and polymer ink for use in printable electronics.

It is clear that Bao intends to use the semiconducing nanotube product for her work in flexible electronics.

"I'm especially happy that this polymer can now be used to sort nanotubes," Bao said. "It merges two very important materials together and makes a hybrid material that could be very useful for printed and flexible electronics."

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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