From the headlines, you’d think all the action in chip making was happening at the industry’s cutting edge, where top manufactures are racing toward the so-called 7-nanometer node. (Guilty as charged.) But there are ways to make better ICs besides forcing them to follow Moore’s Law down to the bitter end.
One solution is emerging from Silicon Valley-based Atomera. The company has developed a single technique that boosts the speed of transistors, lessens the variability between devices on the same chip, and improves the reliability of those devices by keeping them in a youthful state. Atomera expects its technology, called the Mears Silicon Technology (MST), will give chip designers an opportunity to improve their systems without taking an expensive step toward a smaller transistor technology. Consequently, it might allow older semiconductor fabs to stay in production longer. Atomera is even working with leading chipmakers to show a benefit for the most advanced transistor geometries.
Basically, the technique involves burying atom-thin layers of oxygen just below the surface of a transistor’s silicon. This makes the device better in several ways without interfering with the device’s operation, explains Robert Mears, its inventor. “You retain the silicon’s crystalline properties but give it a nudge in a particular direction,” he says. (Incidentally, Mears built the first erbium-doped fiber amplifier, an invention that fundamentally changed the direction of optical fiber communications.)
The oxygen acts as a barrier that sharpens the concentration profile of dopant atoms in silicon. Silicon is only a useful semiconductor because of these dopants, and they determine which type of charge carriers (electrons and holes) forms the current within a transistor.
This sharp dopant profile has the effect of confining the flow of current within the device to a more two-dimensional space. Charge carriers flow faster when confined to a plane, because they are less likely to knock into an obstacle in the silicon crystal. (Such two-dimensional flow is actually the secret to high electron-mobility transistors.) The result is a faster-switching transistor.
The confinement also makes it more difficult for current to leak through the transistor’s gate. The quantum mechanics of the situation make it so that enhancing flow horizontally through the transistor channel has the effect of making vertical flow—from the gate into the channel—that much less likely. Such gate leakage is a major source of wasted power, which led to a fundamental redesign of the CMOS transistor gate back in 2008.
Finally, by sharpening the concentration profile of the transistor dopants, MST reduces variability among transistors on the same chip. That is, there will be less difference from one transistor to another in terms of how much voltage it takes to turn it on, and in how much current flows through it when it’s on. “Customers have seen 20 percent and 40 percent improvement in matching,” says Mears.
Variability is a big deal to designers, because they have to design circuits to work with the worst-performing devices even though there may be many neighboring devices that are much speedier or more power efficient. As transistors shrink, one big source of variability is the number of dopant atoms in a given area. For large transistors this is less of a problem, because they contain thousands of dopant atoms. But small transistors might have only a few hundred. So 10 atoms more here or 20 fewer there will have a noticeable difference in the device’s abilities. (See “The Threat of Semiconductor Variability,” IEEE Spectrum, July 2012 for a better view of this problem.)
A related problem for designers is having to account for how transistors age with use. (See “Transitor Aging,” IEEE Spectrum, May 2011 for why they do that.) So their circuits have to have design margins that account for how a chip’s transistors will perform after years of use.
“The full theory of it is not completely understood at the moment, but because of the steep doping profile, we can keep dopants away from semiconductor-dielectric interface,” which is the location of some aging effects, explains Mears. He believes MST’s aging and variability improvements will be particularly useful for the “sense-amp” circuits that read the state of memory in SRAM and DRAM, and which are particularly sensitive to such changes.
Atomera is counting on the idea that the opportunity to redesign chips with faster, less power-hungry, more uniform transistors without having to pay for another step along the Moore’s Law ladder will be very attractive to a wide range of foundries and other chip makers. “It can be used across all different process nodes—from legacy analog to those still in development now,” says Scott Bibaud, the company’s president and CEO.