MRAM Tech Startup Says Its Device Solves DRAM’s Row Hammer Vulnerability

Spin Memory's vertical gate-all-around transistor could shrink MRAM and other embedded memories

3 min read
Micrograph of vertical channel transistor
Spin Memory's vertical gate-all-around transistor could shrink MRAM and RRAM memory cells.
Image: Spin Memory Inc

Fremont, Calif.-based magnetic RAM startup, Spin Memory, says it has developed a transistor that allows MRAM and resistive RAM to be scaled down considerably. According to the company, the device could also defeat a stubborn security vulnerability in DRAM called Row Hammer.

Spin Memory calls the device the “Universal Selector.” In a memory cell, the selector is the transistor used to access the memory element—a magnetic tunnel junction in MRAM, a resistive material in RRAM, and a capacitor in DRAM. These are usually built into the body of the silicon, with the memory element constructed above them. Making the selector smaller and simplifying the layout of interconnects that contact it, leads to more compact memory cells.

Essentially, transistors are built horizontal to the plane of the silicon. When the device is on, current flows through a channel region between a source and drain. The Universal Selector tilts that geometry 90 degrees. The source is at bottom attached to a conductor buried in the silicon, the channel region is a vertical silicon pillar, and the drain is on top. The gate, the part of the device that controls the flow of charge, surrounds the channel region ion all sides.

The 'Universal Selector' is like an ordinary transistor, but tilted 90 degrees. The 'Universal Selector' is like an ordinary transistor, but tilted 90 degrees. The memory element, usually MRAM, is attached to the drain above the device.Image: Spin Memory Inc.

Such vertical gate-all-around devices are similar to those used to make today’s multilayer NAND flash storage chips. But Spin Memory’s devices span only one layer and are tuned to operate at much lower voltages.

According to the company, the vertical device would improve DRAM array density by 20-35% and allow manufacturers to pack up to five times more MRAM or RRAM memory into the same area.

The selector is part of a trio of inventions Spin Memory is developing to boost MRAM’s adoption. The other two are an improved magnetic tunnel junction, and a circuit design that boosts MRAM’s endurance and read and write speeds, as well as eliminating sources of error. The combination, according to Jeff Lewis, senior vice president of product development, would bring MRAM to a level of performance on par with SRAM, the superfast memory embedded in today’s CPUs and other processors.

A more compact memory cell design.Using the 'Universal Selector' leads to a more compact memory cell design.Image: Spin Memory Inc.

“The use of SRAM as the main on-chip memory is becoming problematic because of its known scalability,” says Lewis. Because it’s just a single transistor and a magnetic tunnel junction, MRAM could one day have a density advantage over SRAM, which is made up of six-transistors. More importantly, unlike SRAM, MRAM keeps its data even when there is no power to the memory cell. Right now, however, MRAM cells are considerably larger than SRAM.  “One of our key objectives was to come up with a smaller cell size for MRAM so that it could have greater attraction as an SRAM replacement.”

With DRAM, the main memory of choice for computers, the Universal Selector has an interesting side-effect: it should make the memory immune to the Row Hammer. This vulnerability occurs when a row of DRAM cells is rapidly charged and discharged. (Basically, flipping the bits at an extremely high rate.) Stray charge from this action can migrate to a neighboring row of cells, corrupting the bits there.   

“Row hammer is one of the leading issues in DRAM reliability and security, and has long been a frustrating plague on the memory industry. As DRAM’s longstanding major disturb problem, row hammering is only becoming more of a problem as cells shrink,” Charles Slayman, a device reliability expert at Cisco Systems, said in a press release.

According to Lewis, the new device is immune to this problem because the transistor channel is outside of the bulk of the silicon, and so it’s isolated from the wandering charge. “This is a root-cause fix for row hammer,” he says.

For use in DRAM, the device would have to be shrunk down considerably, which possible. But improving MRAM is the immediate goal. That will involve optimizing the strength of the drive current and other aspects of the device. Spin Memory engineers will be presenting details of Universal Selector next week at the 31st Magnetic Recording Conference.  

The Conversation (0)

3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

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An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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