IBM has become the first in the world to introduce a 2-nanometer (nm) node chip. IBM claims this new chip will improve performance by 45 percent using the same amount of power, or use 75 percent less energy while maintaining the same performance level, as today's 7 nm-based chips. To give some sense of scale, with 2-nm technology, IBM could put 50 billion transistors onto a chip the size of a fingernail.
The foundation of the chip is nanosheet technology in which each transistor is made up of three stacked horizontal sheets of silicon, each only a few nanometers thick and completely surrounded by a gate. Nanosheet technology is poised to replace so-called FinFet technology named for the fin-like ridges of current-carrying silicon that project from the chip’s surface. The life expectancy of FinFet has been more or less set at the 7-nm node. If it were to go any smaller, transistors would become difficult to switch off: Electrons would leak out, even with the three-sided gates.
One can’t help but sense a bit of one-upmanship in IBM’s development after Taiwan Semiconductor Manufacturing Co. (TSMC) decided to stay with FinFETs for its next generation process, the 3-nanometer node. While IBM’s manufacturing partner, Samsung, does plan to use nanosheet technology for its 3-nm node chips, IBM outdid them both by using nanosheets and going down another step to a 2-nm node.
Row of 2-nm nanosheet devicesImage: IBM
To further enable the chip beyond nanosheets, IBM has used bottom dielectric isolation (BDI) to produce 12-nm gate lengths, a feature representing a first in the industry. BDI involves the introduction of a dielectric layer underneath both the source and drain gate regions. The benefits of implementing a full BDI scheme is to reduce sub-channel leakage, immunity to process variation and power-performance improvement.
Another first for these chips was IBM’s application of extreme-ultraviolet lithography (EUV) patterning to the front-end-of-line (FEOL) where the individual devices (transistors, capacitors, resistors, etc.) are patterned in the semiconductor. After a decade of hand-wringing over whether EUV would ever deliver on its promises, it has in the last few years become a keystone for enabling 7-nm chips. Now, in this latest step in its evolution, EUV patterning has made it possible for IBM to produce variable nanosheet widths from 15 nm to 70 nm.
IBM has also developed a multi-threshold-voltage (Multi-VT) scheme for both system-on-a-chip (SoC) and high-performance computing (HPC) applications. Threshold voltages—also known as gate voltages—are the minimum voltage differential needed between a gate and the source to create a conducting path between the source and drain terminals. Multi-VT schemes leverage gates with different thresholds to optimize for power, timing, and area constraints.
Mukesh KharePhoto: IBM
While these all represent breakthrough developments in enabling 2-nm node chips, it does raise the question of interconnect crowding. In a press conference this week, Mukesh Khare, vice president of Hybrid Cloud at IBM Research in Albany, NY, addressed this question by explaining that this latest announcement is focused primarily on the transistor. According to Khare, the transistor is critical to address questions of scale, especially in scaling the gate length and the power and performance. However, he was quick to acknowledge the importance of interconnect issues.
“Interconnect scaling is equally important as the transistor,” said Khare. “We are continuing to drive the correct scaling for the interconnects as well. That’s part of our full 2-nm technology features.”
Khare was reticent to discuss the specifics of standard cell library density and SRAM, and only offered that it will likely follow the same bench marking that the industry has been tracking with 7-, 5- to 2-nm nodes.
IBM expects this chip design will be the foundation for future systems for both IBM and non-IBM chip players, and the potential benefits of these advanced 2-nm chips will be exponential for today's most advanced semiconductors.
The company anticipates that that 2-nm node could potentially reduce the carbon footprint of data centers. It estimates that if every data center changed their servers to 2-nm-based processors, it could save enough energy to power 43 million homes.
Closer to most of us is what IBM expects this to do our laptops and portable devices’ functions—including quicker processing in applications, easier language translation, and faster 5G or 6G connections.
For those who find daily phone charging annoying, 2-nm node chips will quadruple cell phone battery life vs. 7-nm node chips, which the company says could require users to charge their devices only every third or fourth day, rather than every night.
IBM also anticipates that this may impact autonomous cars by providing faster object detection and reaction.
All of this sounds promising and it may not be that far off. Khare suggested that 2-nm chip modes could be rolling out of fabs as early as 2024.
This article appears in the August 2021 print issue as “Big Blue Gets Small.”
Dexter Johnson is a contributing editor at IEEE Spectrum, with a focus on nanotechnology.