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IBM Extends Graphene to Silicon Scales

The chipmaker has built graphene circuits on 200-mm wafers

2 min read
IBM Extends Graphene to Silicon Scales

Graphene is growing up (or, rather, out). When physicists Andre Geim and Konstantin Novoselov first isolated the speedy two-dimensional material in 2004 using sticky tape, they were lucky to create flakes of the stuff that spanned a few micrometers.

Now, IBM has demonstrated the ability to make integrated circuits on 200-mm wafers coated with a continuous layer of the atom-thick material. The results were reported on Monday at the 2011 International Electron Devices Meeting in Washington, D.C. According to a paper submitted to the conference by Shu-Jen Han of IBM’s T.J. Watson Research Center in Yorktown Heights, New York and colleagues, the demonstration is a “major step in transitioning this promising material from a scientific curiosity into a real technology.”

To create the large wafers, Han and colleagues grew graphene on copper foil from vapor heated to more than 900 degrees C. The team coated this graphene layer with the polymer PMMA and then dissolved away the copper, leaving a bottomless graphene layer that could be picked up and placed onto a silicon wafer.

Before placing the graphene on the wafer, the team etched in deep trenches and filled them with tungsten to create gates. The source and drain regions of each transistor, which are used to pass current through each graphene channel, were built on top of the graphene sheet.

IBM has previously declared an interest in wafer-scale processes, but until now it wasn’t quite clear how far along the research had progressed. Just a few months ago, the company published a paper reporting on a much smaller-scale development: the first integrated circuits made from graphene.

Like earlier devices, the graphene transistors that IBM has built are radio frequency (RF) devices, the sort that are used to build electronics such as digital signal processors. Because graphene has no natural bandgap, its electrons are always in some conductive state. Transistors built from the material can't be switched on and off to create logic. Researchers have a few different tricks that can be used to create a bandgap, but work on graphene-based RF devices is much farther along.

So when will we see graphene-based electronics fully emerge from the lab? All the devices on the wafer are functional, Han says, but “the variation is still pretty large and a lot of them will fall out of spec.” The culprit seems to be graphene quality. The team found that smaller devices on the wafer show better performance than larger devices. They attribute the difference to the fact that larger devices have a higher chance of being built atop a defect, such as a boundary between differently oriented graphene crystals or a wrinkle in the graphene layer created during the transfer process. Ironing those defects out and improving crystal purity may take a bit of time, but considering how far the material's come in less than 10 years, I won't be placing any bets on how long it will take.

Images: IBM/IEDM

 

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
DarkBlue1

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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