DNA Scaffolding Technique Promises Sub-22 nm Lithography

Self assembly and lithography combine to create promising technique that could lead to 6 nm resolution

1 min read

In a paper to be published in next month’s Nature Nanotechnology, Researchers at IBM’s Almaden Research Center and the California Institute of Technology have developed a way to use DNA origami structures as a quasi circuit board or scaffold for precisely assembling components at resolutions as small as 6 nm.

The attractiveness of the process is that it utilizes currently used lithography techniques. Spike Narayan, manager, Science & Technology at the  IBM Almaden Research Center is quoted in the IBM press release:

“The cost involved in shrinking features to improve performance is a limiting factor in keeping pace with Moore’s Law and a concern across the semiconductor industry,” he says. “The combination of this directed self-assembly with today’s fabrication technology eventually could lead to substantial savings in the most expensive and challenging part of the chip-making process.”

The BBC’s coverage of the same story followed Narayan’s quote above with the rather sobering reality that it could take as long as 10 years to see this technology integrated into the semiconductor industry.

Whenever you see the figure “ten years’ used in future projections you could just as easily add another zero to that number. It’s sort of like saying, “Who knows?”

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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