Engineers at Imec and IBM have independently developed new manufacturing processes for making the next decade’s leading chips, they revealed late last year.
These efforts will allow the marriage of silicon wafers and certain exotic materials—compound semiconductors with ingredients from columns III and V of the old periodic table. This mixing of materials holds the key to maintaining the traditional performance improvements associated with Moore’s Law and the shrinking of transistor dimensions.
Both Imec and IBM have built highly efficient transistors with the III-V semiconductor indium gallium arsenide. Electrons can zip through this material six times as fast as they can through silicon. Thanks to this speed, it’s possible to cut a transistor’s operating voltage while maintaining the amount of current flowing through it, thereby trimming power consumption.
Engineers at Imec, in Leuven, Belgium, revealed their breakthrough first, announcing in November that they had taken an industry-standard 300-millimeter silicon wafer and formed fin-shaped field-effect transistors. FinFETs are the type of 3-D transistor deployed in the most advanced microprocessors. The Imec devices replaced the FinFET silicon channel with one made of indium gallium arsenide.
Dean Freeman, an analyst at Gartner, believes that this type of channel could make its debut as early as the 7-nanometer node, the generation of chips due to market in as little as four years. “I don’t want to put words in Intel’s mouth, but there is a potential that we could see this FinFET technology emerge into very-high-end servers,” he says.
Smartphones could also benefit, because the altered channels would increase battery life and reduce the number of chips in a phone. Today, in most cases, a mobile phone uses a III-V chip to amplify wireless signals and a separate silicon chip for data processing. The recent breakthroughs could let a single chip carry out both tasks.
Imec forms its FinFETs by taking a silicon wafer and etching trenches into it that are just tens of nanometers wide. Each trench is filled with indium phosphide before indium gallium arsenide is added to produce the protruding fin of the transistor.
Using a trench reduces crystal defects in the transistor channel. Depositing indium phosphide on silicon always leads to defects, because of the 8 percent difference in the average spacing of the atoms in these two crystals. However, these defects—missing planes of atoms aligned at about 45 degrees to the wafer surface—terminate at the trench walls, enabling the growth of high-quality material near the wafer surface.
“I do not want to claim that [the channel] is completely defect-free,” says Aaron Thean, director of Imec’s R&D program on logic devices, “but it’s definitely good enough for the transistor to work now.”
At the IBM Zurich Research Laboratory, engineers use entirely different processes. Their approach, which Lukas Czornomaz described at the IEEE International Electron Devices Meeting (IEDM) held in Washington, D.C., in December, begins by forming a substrate composed of a 6-nm-thick film of indium gallium arsenide and an 8-nm-thick layer of silicon germanium, separated by a thin insulator.
Introducing silicon germanium allows the production of CMOS circuits because it enables the formation of high-speed transistors based on the movement of holes—essentially the positive counterparts to electrons. With the new process, “we demonstrate, for the first time, a hybrid, high-mobility CMOS circuit on insulator, where we have small n- and p-transistors based on these two materials on the same substrate,” says Czornomaz.
He claims that such engineered substrates offer three benefits for integrated-device manufacturers: very low leakage currents, thanks to the insulating layer beneath the devices; relatively minor adjustments to the foundry processes, because the challenges of introducing new materials are shifted to the substrate supplier; and tremendous freedom for the circuit designer to select the size and position of the transistors. In Imec’s trench scheme, III-V semiconductors and silicon germanium are present only in defined areas of a wafer, but with IBM’s approach, these materials are everywhere.
The engineers at IBM Zurich used their process to build an inverter operating at 0.5 volt. That’s 0.3 V less than the voltage used in state-of-the-art silicon FinFETs, leading to 60 percent lower power consumption. Imec’s transistors also operate at 0.5 V, delivering a performance that Thean describes as “almost as good” as a silicon equivalent.
In separate research, Czornomaz’s colleagues at IBM’s T.J. Watson Research Center, in Yorktown Heights, N.Y., appear to have done even better than that. “The intrinsic performance of [our] device is better than silicon, if we compare the same dimensions,” says Yanning Sun of IBM Watson. At IEDM, she detailed the results of indium gallium arsenide transistors with a 30-nm gate length—about the dimensions of a leading-edge transistor from 2010. The devices were formed on an indium phosphide substrate using CMOS-compatible processes.
At IBM Watson and at Imec, engineers will now try to shrink their transistor dimensions to enable a true comparison with state-of-the-art silicon. Meanwhile, the team at IBM Zurich will aim to increase the size of the engineered wafer from 100 to 300 mm and to build a static RAM cell, a compact, six-transistor memory cell common on microprocessors. “If someone can show 0.5-volt SRAM on silicon germanium and III-Vs, it’s a big step ahead,” says Czornomaz.