UCLA Builds Fastest Graphene Transistor Yet

Operation at terahertz frequencies is in sight

1 September 2010—Graphene promises to be the basis for future circuits that can operate far faster than silicon chips, but first researchers have to devise the best way to build them. The latest contender comes from the University of California, Los Angeles, where scientists and engineers have used a nanowire to build a transistor based on graphene.

The resulting field-effect transistor switches at the highest speed reported so far: 300 gigahertz in a device with a channel length (the distance between the source and the drain) of 140 nanometers. That’s roughly twice as fast as the best silicon metal-oxide-semiconductor field-effect transistor of similar proportions and comparable to transistors made of indium phosphide or gallium arsenide, which are expensive compound semiconductors.

”It has the potential to get into the terahertz range,” says Xiangfeng Duan of the California NanoSystems Institute at UCLA, who reported the design online in Nature this week. ”Eventually this should be a relatively easy process, and with some modifications it could be a scalable process.”

Graphene is a single atomic layer of carbon atoms arranged into hexagons. Because of its electronic structure, charge carriers move through it with great ease, allowing for far faster circuits than silicon. But the conventional process of building the electrodes that act as the transistors’ gates, sources, and drains introduces defects into the carbon lattice, slowing down the flow of charge. The UCLA group got around this problem by using a nanoscale wire as both a component of and a template for the transistor.

First they grew a nanowire of cobalt silicide with a thin, insulating shell of aluminum oxide. Then, using a ”dry transfer” process that didn’t lead to a chemical reaction, they laid the nanowire on top of a layer of graphene to form the transistor’s gate. Next, they shaved away part of the aluminum oxide to provide electrical contact between the wire’s conductive core and the thin layers of gold and titanium they had deposited at one end of the wire to act as the gate electrode. They then deposited a gold-titanium source on one side of the nanowire and a drain of the same material on the other side. They followed that with a coating of platinum running from the source, over the wire, to the drain. Because the platinum was just 10 nm thick, it broke apart at the wire, creating a separate electrode on either side of the wire, both in contact with the graphene.

An advantage to this design, Duan says, is that it eliminates any gap between the gate and the source and drain electrodes. Any part of a transistor channel not covered by the gate is not modulated by the input voltage, decreasing the efficiency of the transistor. When the device is large, a gap of a couple of hundred nanometers makes little difference, but when the channel gets very small, even a small gap takes up a sizable percentage of the channel and becomes a big problem. ”Our approach allows us to make a perfect alignment between the source and gate and drain,” Duan says.

The channel length is defined by the diameter of the nanowire, which in the transistors built by Duan’s team was 100 to 300 nm. That’s relatively thick, and Duan would like to get the diameter under 100 nm. He hopes to get to about 50 nm, which would allow him to build devices that could reach terahertz speeds.

Earlier this year, a team from IBM, led by Phaedon Avouris and Yu-Ming Lin, also reported a high-speed graphene transistor. They got around the defect problem by using a thin polymer layer as an insulator. They agree that the UCLA team has achieved the highest speeds so far. ”This is very nice work that clearly demonstrates the high potential of graphene for applications in high-frequency devices,” the two wrote in an e-mail.

But they added that Duan’s method of obtaining the graphene, by flaking off a layer from a piece of graphite, won’t translate well to high-volume production. ”It is not the same as growing wafer-scale graphene and using proven lithographic and deposition techniques to fabricate the transistor arrays that we developed and continue to improve,” they wrote.

Duan, though, says this was only a proof-of-concept demonstration and that his nanowire approach could be adapted to processes more suitable for production.

About the Author

Neil Savage writes about nanotech, optoelectronics, and other technology from Lowell, Mass. In the July 2010 issue he reported on the adoption of Innovative Silicon’s capacitorless dynamic RAM technology by Hynix.

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