IEEE Meeting Plays Host to the Nanomaterials that Aim to Displace Silicon

The place to be this first week of December, if you follow nanotechnology in electronics, is at the IEEE International Electron Devices Meeting (IEDM) in Washington, DC. Hopefully with better planning on my part I can find myself at next year’s meeting.

The news from this year’s event has contained some real eye-openers. Intriguingly, at least some of the news centers around research that is a reaction to Intel’s introduction of its 3D 22-nm Tri-Gate transistor.

In collaborative research between Purdue and Harvard Universities,  researchers are looking into new materials for these 3D chips that will improve electron mobility in these devices and enable the further advancement of this 3D approach.

The researchers are focusing their search on III-V materials, in particular, indium-gallium-arsenide, with which they will make nanowires.

"Industry and academia are racing to develop transistors from the III-V materials," said Pied “Peter” Ye, a professor of electrical and computer engineering at Purdue in the story that covers this research for the university news service. "Here, we have made the world's first 3-D gate-all-around transistor on much higher-mobility material than silicon, the indium-gallium-arsenide."

According to Ye, as the 3D Tri-Gate transistor moves from its current gate length down to 14nm by 2015, silicon will not be able perform. However, Ye believes that nanowires made from III-V materials will get us to the 10nm range.

There’s another approach from the IEDM that is aiming at the 10nm threshold that also has been getting a lot of coverage. Publications from the New York Times to the Wall Street Journal have devoted pixels this week to the work IBM is doing with using carbon nanotubes to create transistors that should keep them performing at and below the 10nm threshold.

The IBM researchers reported at the IEDM on their work at making “the first transistor with sub-10 nm channel lengths, outperforming the best competing silicon-based devices at these length scales.”

According to the IBM press release that went out at the time of the IEDM presentation: “…this breakthrough demonstrates for the first time that carbon nanotubes can provide excellent off-state behavior in extremely scaled devices-- better than what some theoretical estimates of tunneling current suggested.”

IBM’s work with carbon nanotubes here was also accompanied with more reports on the company’s use of graphene to create a CMOS-compatible device for wireless communications.

It would seem that IBM continues to vigorously pursue both graphene and carbon nanotubes to realize the merciless demands of Moore’s Law.

How ever the graphene vs. carbon nanotubes story ultimately plays out, one thing is becoming clear that architecture alone is not going to guide electronics below 10nm and replacing silicon will be required. We'll just have to see which of the nanomaterials wins the day.

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Nanoclast

IEEE Spectrum’s nanotechnology blog, featuring news and analysis about the development, applications, and future of science and technology at the nanoscale.

 
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