TSMC R&D Chief: There’s Light at the End of the Chip Shortage

The IEEE award recipient talks about the next generation of chips

4 min read

A photo of a man in a blue suit and glasses in front of a logo that says “tsmc”

Yuh-Jier Mii started on the ground floor of Taiwan Semiconductor Manufacturing Co. in 1994 as a fabrication integration manager. Today he’s one of the Hsinchu-basedcompany’s leaders as senior vice president of research and development. During his nearly 30 years at TSMC, he has been involved with the creation of denser and denser integrated circuits.

The IEEE member is in charge of R&D for new chips built using TSMC’s 3-nanometer process node, expected to go into production later this year. (The commercial term nanometer refers to a new, improved generation of silicon semiconductor chips.)

The world’s largest contract chip manufacturer credits Mii with helping it maintain technology leadership in the foundry segment of the global semiconductor industry.

For his “leadership in developing industry-leading foundry logic process technologies and open innovation design platforms,” Mii is being honored with the 2022 IEEE Frederik Philips Award. He shares the award with his colleague Cliff Hou, TSMC’s senior vice president of technology development and corporate research. The award is sponsored by Philips.

“It is my great honor to have received this award,” Mii says. “I found out there were many outstanding leaders in this industry who have also received this award, such as Dr. Gordon Moore. This is also special for me because I received it with Cliff, who is doing the design part of the work. We work together to make the technology useful for our customers.”


Growing up, Mii was interested in physics, astronomy, and all kinds of science-related subjects, he says. Like most budding engineers, he liked to tear things apart to see how they worked.

“By nature, I was interested in doing engineering,” he says. “Growing up in Taiwan, the environment encouraged people to become scientists or engineers.”

Mii earned a bachelor’s degree in electrical engineering from National Taiwan University, and his master’s and Ph.D., also in EE, from the University of California, Los Angeles. He was hired in 1990 as a researcher at IBM’s Thomas J. Watson Research Center, in Yorktown Heights, N.Y. During his four years there, he worked on IBM’s 0.1-micrometer CMOS technology which, he says, had similar dimensions to the 90-nanometer technology he later worked on at TSMC.

Mii left IBM to join TSMC. It was, he says, a “big and bold move in many people’s points of view—going from pure research to process integration in the manufacturing fab. But I think that was a good move for me and a very rare opportunity. I learned how fab operators work, what’s in their minds, and what’s required to make a technology manufacturable.”

“It’s important for us to get the talent and the wisdom from the whole world, not just from the team in Taiwan.”

After learning the ropes as a fab integration manager, he was promoted to fab deputy director. Then, in 2011, he was moved to R&D because several people had left, he says. His time as a researcher at IBM was about to pay off.

“Because I had some past research experience, I was transferred to R&D and managed the 90-nanometer program, and then the 40-nm,” he says.

Later he was put in charge of the company’s advanced technology development. The role involved defining the process technology and leading the team that would develop it for manufacturing nanotechnology-based semiconductor chips. They were the smallest transistors produced at the time.

Like most top leaders, Mii attends a lot of meetings. However, he’s still enthusiastic about diving in to help solve problems.

“It’s exciting when you see a big problem and you find a way to resolve it,” Mii says. “Thanks to my team, which is quite capable, I don’t need to get involved in the details of problem-solving, but it’s always intriguing and exciting to find solutions.”


One of Mii’s most important challenges, he says, is determining the options for each technology that will bring the most value to TSMC’s customers as well as deliver the solution in a predictable schedule. That was certainly true of the upcoming 3-nm node, which will succeed the 5-nm node just two and a half years later. The 3-nm node is slated to hit the market later this year, and he’s already working on the 2-nm version.

“We are approaching atomic scale,” Mii says. “Before, we could achieve the next-generation node by fine-tuning the process, but now for every generation we must find new ways in terms of transistor architecture, materials, processes, and tools. In the past, it’s pretty much been a major optical shrink, but that’s no longer a simple trick.”

Early in his career, developing a new process technology meant just shrinking the transistor using better lithography. But it requires more innovation now, he says.

Another challenge, he says, is finding enough talented engineers.

The semiconductor shortage is still another hurdle he has had to face. In his personal opinion—not necessarily that of TSMC—it is going to take two to three years to bring new fabs online to resolve the situation. He partly blames the COVID-19 pandemic for disrupting the global economy, but the growing pervasiveness of electronics in daily life is also causing a surge in semiconductor demand.

He says the industry missed signs that demand was growing. However, he says, the field learned a lot from the situation, and he expects it will do better in the future.

“Right now, the industry is investing a tremendous amount of capital into building extra capacity to solve this chip shortage problem,” Mii says. “We have a much clearer picture of future demand today than we had two years ago.”


MII joined IEEE as a grad student at UCLA.

“As an EE student, it was natural to join IEEE,” he says, “because that’s the portal for people to exchange information and learn.”

He’s still in IEEE to learn, he says: “We always go to the conferences to exchange both information with others and also learn from new things.” These days, he acknowledges, he doesn’t have the time to attend many conferences, so instead he sends his engineers. After they return, he holds a debriefing session to learn about advancements and what direction the industry is headed.

“Developing technology by ourselves is not enough,” Mii says. “In my leadership role, it’s important for us to get the talent and the wisdom from the whole world, not just from the team in Taiwan.”

The Conversation (2)
Yau-Wah Sam
Yau-Wah Sam22 Mar, 2022

"The commercial term nanometer refers to a new, improved generation of silicon semiconductor chips" -- referring to the term "nanometer" as a silicon generation is not what I'd expect from an IEEE publication. Perhaps the description was intended for "process node"?

1 Reply