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The High School Student Who’s Building His Own Integrated Circuits

Sam Zeloof has turned his parent’s garage into a 1970s-era fab

3 min read
Photo of Sam Zeloof
Photo: Beth Deene

Electronics enthusiasts like being able to make things themselves. In IEEE Spectrum’s Hands On column, we’ve detailed how readers can make their own solder reflow ovens, conductive ink, and synthetic aperture radars. But making DIY integrated circuits seemed impossibly out of reach. After all, building a modern fab is astronomically expensive: For example, in 2017 Intel announced it was investing US $7 billion to complete a facility for making chips with 7-nanometer-scale features. But Sam Zeloof was not deterred. This 17-year-old high school student has started making chips in his garage, albeit with technology that’s a few steps back along the curve of Moore’s Law.

Zeloof says he has been working on his garage fab, located in his home near Flemington, N.J., for about a year. He began thinking about how to make chips as his “way of trying to learn what’s going on inside semiconductors and transistors. I started reading old books and old patents because the newer books explain processes that require very expensive equipment.”

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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