Researchers at Fudan University in Shanghai, China have leveraged two-dimensional (2D) materials to fabricate a relatively new gate design for transistors that may fill the gap between volatile and non-volatile memory.
The result is what the researchers are dubbing a “quasi-non-volatile” device that combines the benefits of static random access memory (SRAM) and dynamic random access memory (DRAM). The new device will make up for DRAM’s limited data retention ability and its need to be frequently refreshed and SRAM’s high cost.
In research described in Nature Nanotechnology, the Chinese researchers leveraged a gate design that has been gaining popularity, recently called semi-floating gate (SFG) memory technology. The SFG gate design is similar to a typical field effect transistor except that SFG transistor can “remember” the applied voltage from the gate.
The researchers have shown that the 2D SFG memory they have fabricated has 156 times longer refresh time (10 seconds) than DRAM (64 milliseconds), which saves power, and ultrahigh-speed writing operations on nanosecond timescales (15 nanoseconds), which puts it on par with DRAM (10 nanoseconds). This new device also boosts the writing operation performance to approximately 106 times faster than other memories based on 2D materials.
These improvements to refresh time and writing operations suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption demanded by frequent refresh operations, enabling a high-speed and low-power random access memory.
The first floating gate transistor was made in 1967 and since then has become a mainstay of nonvolatile memory technology. However, the writing/erasing speed of a floating gate transistor is around one millisecond, making it slower than the CPU, prohibiting its use where a high writing speed is needed.
The researchers saw that there was a chance to improve the performance of a floating gate transistor because so much of its performance is based on its band structure and the interface between the transistor’s channel and its gate dielectric.
Increasingly, research has shown that through the careful layering of different types of 2D materials—alternating between insulators and conductors—it’s possible to tailor the band structure of these hybrid 2D materials. These layered materials, known as van der Waals heterostructures because van der Waal forces hold each layer in place, can snap into place like a LEGO brick despite having different lattice structures. This stacking capability makes it easier to tailor the electronic properties of the heterostructures to create functional devices.
“Two-dimensional materials have abundant band structures, which provides much more freedom in the design of a floating gate transistor and allows for the ability to achieve better performance,” said Peng Zhou, a professor at Fudan University and co-author of the research. “What’s more, the perfect interface of 2D materials can improve the reliability of a floating gate transistor.”
The device architecture consists of a channel made from the 2D material tungsten diselenide. A combination of the 2D semiconductor molybdenum disulfide with the insulator hexagonal boron nitride serves as the semi-blocking layer. The heterojunction between molybdenum disulfide and tungsten diselenide serves as the p–n-junction switch.
To put this work in context, you need to see it in terms of the metal-oxide–semiconductor field-effect transistor (MOSFET): the fundamental element of most integrated circuits. MOSFETs are basically a switch in which a voltage from the gate turns on or off a flow of current between the source and the drain.
But anyone who has followed the challenges brought on by Moore’s Law over the last 20 years knows that as the dimensions of these devices have shrunk, it becomes increasingly difficult for the gates of a MOSFET to stop the flow of electrons.
While some have shown that one-nanometer gate dimensions are possible in these devices, it’s still proving an engineering challenge to get past the five-nanometer limit, at which point electrons start pulling their trick of tunneling right through the gate material.
With the SFG architecture, electron tunneling is turned from a disadvantage into an advantage. This is achieved by the SFG design including a tunneling field-effect transistor that couples the positively doped floating gate to the negatively doped drain region. The charge stored on the SFG is used to shift the voltage threshold for switching the transistor, which in turn speeds up its operation and lowers its power consumption.
Zhou believes that the main challenge in making this device commercially viable is achieving wafer scale production of 2D materials.
Zhou added: “If we can get wafer-scale uniform 2D materials, the 2D SFG quasi-nonvolatiole memory can realized by industry.”