While there may be some quibbling about what really is the smallest transistor ever fabricated, an all-star lineup of U.S.-based researchers has laid a legitimate claim to having fabricated one that is at, or at least very near, the top of the list. And this one enjoys the relatively rare quality of having the potential to become more than just a lab curiosity.
With a physical gate length of only one nanometer, this latest transistor, made from a combination of molybdenum disulfide and carbon nanotubes, not only shatters the 20-nm gate length of state-of-the-art transistors currently on the market, but also surpasses the theoretical limit of five nanometers for the gate length of silicon-based transistors. While silicon transistors may stop shrinking by 2021, this research shows that transistors based on nanomaterials may still have some way to go in their miniaturization journey.
In research described in the journal Science, researchers from the U.S. Department of Energy’s Lawrence Berkeley National Laboratory, Stanford University, and the University of Texas at Dallas built their experimental transistor with molybdenum disulfide for the channel material, and single-walled carbon nanotubes as the gate material.
This combination of nanomaterials offers a real benefit over silicon as gate dimensions of transistors shrink. A quick refresher is in order. Transistors consist of three main elements: a source, a gate, and a drain. Charge passes between the source and the drain through the channel. The gate is used to open or close the flow of those charges.
Silicon is actually preferable to molybdenum disulfide as the channel material in most cases, because the electrons flowing through the silicon channel encounter less resistance than they do in molybdenum disulfide. Unfortunately, physics starts to bite back when the gate dimensions get down to five nanometers. It’s at this point that the electrons pull a little quantum trick, tunneling through gate material. The result: The flow of electrons can no longer be turned on and off, and there goes your digital logic capabilities.
But the electrons that were slowed down in molybdenum disulfide, which had been a detriment at dimensions above 5 nm, become a benefit when gate lengths go below those dimensions. This slowing down of electrons in molybdneum disulfide makes them easier to control.
The next issue researchers faced was figuring out what material to use in making the gate. Crafting a gate only 1 nm wide is excruciatingly difficult with traditional lithographic techniques. As a way to bypass that entire issue, the researchers turned to carbon nanotubes.
“It is hard to fabricate 1-nm metal gates, especially in an academic research lab,” explained Ali Javey, lead principal investigator of the Electronic Materials program in Berkeley Lab’s Materials Science Division, in an e-mail interview with IEEE Spectrum. “Carbon nanotubes provide that dimension readily. They are excellent conductors with no edge roughness (thus resulting in devices without any gate edge roughness).”
This kind of research often leads to inflated expectations of what it all really means, and Javey has been quick to temper expectations. “It’s a proof of concept,” said Javey in a press release. “We have not yet packed these transistors onto a chip, and we haven’t done this billions of times over. We also have not developed self-aligned fabrication schemes for reducing parasitic resistances in the device.”
Nonetheless, there is justifiable enthusiasm at what this means for the five-nanometer-gate-width limit that was quickly becoming a showstopper. This research at least shows that there could be a way forward.
Javey told IEEE Spectrum that the group plans to address the following issues in future research:
Large-area, controlled growth of molybdenum disulfide needs further improvement. This is an important research topic that has seen major progress in recent years due to the work of various research groups around the world, but more progress is still needed. In addition, schemes (including self-aligned source and drain electrodes fabrication in respect to the gate, and chemical doping of the contact regions) need to be developed that will lower the parasitic resistances and enhance the ON current of the devices.
This story was corrected on 10 October 2016.