New Lithography Makes Smallest SRAM Yet

A radically different chipmaking process could pave the way for future generations of microprocessors

3 min read

30 November 2009 A new type of lithography, which uses an electron beam to spark a chemical reaction, could provide a cheaper way to build the incredibly tiny transistors that the chipmaking industry will require in a few years. Researchers from Taiwan and the University of California, Berkeley, say they've made static random access memory (SRAM) that anticipates 16-nanometer chip features with a new process called nano injection lithography.

Hou-Yu Chen and his colleagues from National Nano Device Laboratories, in Taiwan, will present their work next month at the International Electron Devices Meeting (IEDM) in Baltimore. They say their technique may provide an alternative to lithography that relies on extreme ultraviolet light (EUV), which still is beset by problems and could be extremely expensive.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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