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Nanowire Transistors Could Let You Talk, Text, and Tweet Longer

Transistors with compound-semiconductor nanowires could consume less power than today’s silicon FinFETs

6 min read
Nanowire Transistors Could Let You Talk, Text, and Tweet Longer
Bridging The Gap: Germanium nanowires are suspended across a gap in this transistor.
Image: Purdue University

We cherish our smartphones for delivering entertainment and information on the go, but their need for daily charging is a problem. Battery life can’t get any shorter than it is today. (Well, it could, but consumers wouldn’t be happy about it.) So when new smartphone models come on the market with microprocessors based on the latest foundry process, the increase in the number of transistors in the chips should be balanced by a reduction in the power that each transistor consumes.

For the remainder of the decade, this power reduction per transistor can be accomplished with today’s workhorse device: the silicon FinFET. (It’s so named because the channel through which current flows is shaped like a vertical fin.) But continuing progress further into the future will require an overhaul of the transistor’s architecture: If the devices unveiled in December at the IEEE International Electron Devices Meeting (IEDM) are an indication, that overhaul will see the FinFET’s silicon fin shrink vertically to become a nanometers-wide wire made from semiconductors other than silicon.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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