Nanoimprint Lithography Aims to Take on EUV

In September, Canon shipped the first commercial version of a technology that could one day upend the making of the most advanced silicon chips. Called nanoimprint lithography (NIL), it’s capable of patterning circuit features as small as 14 nanometers—enabling logic chips on par with AMD, Intel, and Nvidia processors now in mass production.

The NIL system offers advantages that may challenge the US $150 million machines that dominate today’s advanced chipmaking, extreme ultraviolet (EUV) lithography scanners. If Canon is correct, its machines will eventually deliver EUV-quality chips at a fraction of the cost.

The company’s approach is entirely different from EUV systems, which are made exclusively by Netherlands-based ASML. The Dutch company uses a complex process that starts with kilowatt-class lasers blasting molten droplets of tin into a plasma that glows with a 13.5-nanometer wavelength. This light is then steered through a vacuum chamber by specialized optics and bounced off a patterned mask onto a silicon wafer to fix the pattern onto the wafer.

In contrast, Canon’s system, which was shipped to Defense Department–backed R&D consortium the Texas Institute for Electronics, seems almost comically simple. Put simply, it stamps the circuit pattern onto the wafer.

Nanoimprint Lithography: Smaller, Cheaper

NIL starts with a process that’s like photolithography’s. It writes a pattern on a “mask” using a focused beam of electrons. In EUV, this pattern is captured on a mirror and is then reflected onto the silicon. But in NIL, a “master mask,” or mold, made of quartz is used to create multiple replica masks, also made of quartz.

The replica mask is then pressed directly onto the surface of a wafer, as though it were a stamp, that’s been coated with a liquid resin called a resist. Ultraviolet light from a mercury lamp—the kind used in chipmaking back in the 1970s—is then applied to solidify the resin and allow the mask to be removed from the wafer. Thus, the same pattern from the master mask is stamped onto the resist on the silicon. And just as in photolithography-based chipmaking, that pattern guides the series of etching, deposition, and other processes needed to create transistors and interconnects.

“This looks to be a simple yet clever method for advancing light-source-free nanolithography capable of high-accuracy patterning,” says Ahmed Hassanein, leader of the Center for Materials Under Extreme Environment at Purdue University, in Indiana, and an expert in EUV light sources. “The system also has the advantage that it uses less power and should be cheaper to purchase and operate compared to EUV systems.”

Canon claims that, compared to EUV, this direct-contact method requires fewer steps and tools, resulting in a simpler process that’s less costly to operate. For instance, compared to an EUV system employing a 250-watt light source, Canon estimates NIL consumes just one-tenth the energy.

In addition, NIL takes up less of the extremely valuable real estate on the fab’s clean-room floor. Today’s EUV systems are as big as double-decker buses—about 200 cubic meters. But a cluster of four NIL systems occupies less than half that volume (6.6 by 4.6 by 2.8 meters)—though a mask-replication tool taking up another 50 cubic meters is also required.

20 Years to Commercial NIL

But such simplicity comes following a long, costly development process. More than two decades ago, several research labs had already begun developing NIL technology when Canon began its effort in 2004. In 2014, to speed up progress, Canon acquired Molecular Imprints Inc. (MII) based in Austin, Texas, an early leader in the technology. Renamed Canon Nanotechnologies, the subsidiary now serves as a U.S.-based R&D center for the development of NIL.

Yet even with the addition of MII to Canon’s R&D tool chest, it has taken 20 years to bring the technology to market. During that time, Canon had to leap several high engineering hurdles, Kazunori Iwamoto, deputy chief executive of Canon’s Optical Products Operations, told IEEE Spectrum at the NIL production site in Utsunomiya, 100 kilometers north of Tokyo.

In most chipmaking, the resist, which is the polymer resin that holds the circuit pattern, is coated evenly across the wafer surface. But that wouldn’t work for NIL because excess resin can exude from under the mask during the stamping and interfere with the next imprint operation, resulting in defects. So instead, Canon drew on its inkjet printing know-how to apply the resist in optimum amounts to match the circuit pattern. Additionally, the capillary force of the resist was optimized to draw the material into the mask’s etched pattern on contact.

Canon also had to prevent air bubbles from getting between the wafer and the mask during imprinting, which would interfere with the tool’s ability to align the mask to any circuit features already on the wafer. The answer was to design a bendable mask that’s thinner in the center. During stamping, pressure is first applied to the middle of the mask, which pushes the center outward to make contact with the resist first. Contact between the two surfaces then continues radially outward, forcing the air away and out at the edges. It’s not unlike what you might do to avoid creating an air bubble when applying a screen protector to a smartphone.

Besides dealing with particulate contamination by developing environmental control technology, the alignment problem was perhaps the biggest headache.

When layers of circuit patterns are imprinted one on top of the other, precise overlay control is essential to ensure that the vias, vertical connections between layers that transmit signals and power, are properly aligned. The NIL process allows for some wiggle room, but working at the nanometer level means alignment errors can easily occur. For instance, they can arise from variations in wafer flatness and surface features, imprecise wafer and mask placement, and deformation of the mask shape during imprinting. To minimize such distortions, Canon uses a range of mostly automated techniques. These include maintaining strict control of the operation temperature, applying piezoelectric force to correct mask-shape deformation, and applying heat from a laser to expand or contract the wafer and bring it and the mask more into alignment.

“We call this proprietary technology High Order Distortion Correction,” says Iwamoto. “Applying it, we can now overlay circuit patterns with a precision in the order of 1 nm.”

The Step and Stamp World of NIL

With all those problems behind them, engineers at Canon have produced a relatively straightforward lithography process. It begins by creating a master mask. Like other photolithography masks, this is made by etching a pattern using electron-beam lithography. The master mask size is 152 by 152 millimeters, and the patterning area of the master mask—which contains the raised patterns of the circuit design to be printed—measures 26 by 33 mm.

From this master mask, multiple replica masks with recessed patterns are fabricated. Each replica mask can then produce up to 80 lots, with each lot comprising 25 wafers. So one replica can make one layer of circuitry for 2,000 wafers.

To illustrate NIL’s lower cost of ownership, Iwamoto compares it with an advanced argon fluoride immersion lithography system—the predecessor to EUV lithography and still in wide use—set up for producing a dense array of 20-nm-wide contact holes. For the same output, an NIL system working at 80 wafers per hour (wph) can reduce cost of ownership by 43 percent, says Iwamoto. And Canon is targeting a 100-wph scheme capable of producing 340 lots per replica mask by further reducing particulate contamination, improving the quality of the resist, and refining and optimizing the NIL workflow. Achieving this, cost of ownership versus immersion lithography would drop to 59 percent, Iwamoto estimates.

Early Adopters?

Despite the potential advantages, it will be no easy matter to tempt device makers already heavily invested in mainstream EUV to add a different kind of lithography system to their operations.

“EUV has established itself as the mainstream technology over the past decade,” says Hassanein. “It’s overcome many challenges and is capable of high productivity and has a path to produce even smaller patterns. If NIL is to compete, it will need to accelerate production capacity, increase the lifetime of molds, improve particle and debris management, and boost throughput.”

But first, the technology has to get its foot in the factory door. Iwamoto says that after receiving several inquiries from potential customers both in Japan and abroad, they are holding discussions and providing demonstrations of NIL. Aside from shipping the first commercial system to the Texas Institute for Electronics, Canon says Kioxia (formerly known as Toshiba Memory) has been testing NIL systems for several years, and it is now evaluating the process for producing prototype memory chips.

Iwamoto also notes Canon is maintaining an aggressive NIL application road map. Starting in 2028, it aims to produce high-resolution masks that can produce 3D NAND flash memory with a 20-nm line width and 5-nm overlay accuracy. For DRAM, the target is a 10-nm line width with a 2-nm overlay, while logic devices are planned to reach an 8-nm line width and a 1.6-nm overlay. Should those targets be realized in that time frame while also advancing wafer throughput, NIL could become an appealing alternative to EUV, especially for applications where precision and cost efficiency are critical.

This article was updated on 10 January 2025 to clarify the dimensions of Canon’s master mask.