When data is accessed at very high speed in dynamic random-access memory (DRAM) cells (above 1 gigahertz), data corruption can occur. This phenomenon, known as a row hammering (RH) fail, basically means that there has been data corruption due to interference among neighboring DRAM cells.
These RH fails present a serious reliability concern because they’re so difficult to catch during product testing. If not caught, they can lead to computer system failures—like the “blue screen of death”—that have been the bane of computer users for years.
It appears that metallic nanoparticles may be the cure to this long-standing problem. Researchers from the Indian Institute of Technology (IIT) Roorkee, in India, and chip producing equipment giant Applied Materials in Santa Clara, Calif., have joined forces to tackle the issue. They reported in the journal IEEE Electron Device Letters that adding metallic nanoparticles to DRAM could eliminate row hammering in both high-volume DRAM cells and the latest state-of-the-art technology.
While this research was conducted in computer simulation rather than in physical experiments, the researchers believe that it is possible to do this in the real world despite some remaining challenges. “The placement of metallic nanoparticles through a lithographic process step is slightly critical,” said Sanjeev Manhas, associate professor at IIT and coauthor of the research. “Introducing the metal nanoparticles at the correct location is the main challenge, but with the state-of-the-art nanofabrication methods, it is certainly doable.”
The IIT Roorkee team and their collaborator in this research, Arvind Kumar, a member of the technical staff at Applied Materials, introduced nanoparticles into the gate of the access transistor, which has a different work function from that of the gate electrode. The work function difference introduces an energy valley between neighboring cells in the channel region. These valleys prevent diffusion of electrons from the aggressor cell to the victim cell, which strongly diminishes the prevalence of row hammer fail.
The researchers believe that the introduction of nanoparticles into DRAM gate stack engineering is a novel technique that could even be extended to digital logic technologies. In looking ahead to how this technique could actually become part of DRAM, the researchers have suggested possible steps whereby nanoparticles could be introduced selectively.
Kumar added: “It will require additional steps in the conventional DRAM fabrication process flow. Memory manufacturers such as Samsung, Micron, Hynix, and others may find this idea [to be] an interesting process solution for nanoparticle engineered gate stacks at a low cost.”
Dexter Johnson is a contributing editor at IEEE Spectrum, with a focus on nanotechnology.