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Metallic Nanoparticles Come to the Rescue of DRAM

The addition of nanoparticles into DRAM eliminates interference between neighboring cells

2 min read
Figure from the paper showing the doping contour of the RCAT-DRAM structure used to simulate RH (left) and Id-Vg calibration with reported data (right).
Figure from the paper showing the doping contour of the RCAT-DRAM structure used to simulate RH (left) and Id-Vg calibration with reported data (right).
Image: IIT Roorkee/Applied Materials/IEEE Electron Device Letters

When data is accessed at very high speed in dynamic random-access memory (DRAM) cells (above 1 gigahertz), data corruption can occur. This phenomenon, known as a row hammering (RH) fail, basically means that there has been data corruption due to interference among neighboring DRAM cells.

These RH fails present a serious reliability concern because they’re so difficult to catch during product testing. If not caught, they can lead to computer system failures—like the “blue screen of death”—that have been the bane of computer users for years.

It appears that metallic nanoparticles may be the cure to this long-standing problem. Researchers from the Indian Institute of Technology (IIT) Roorkee, in India, and chip producing equipment giant Applied Materials in Santa Clara, Calif., have joined forces to tackle the issue. They reported in the journal IEEE Electron Device Letters that adding metallic nanoparticles to DRAM could eliminate row hammering in both high-volume DRAM cells and the latest state-of-the-art technology.

While this research was conducted in computer simulation rather than in physical experiments, the researchers believe that it is possible to do this in the real world despite some remaining challenges. “The placement of metallic nanoparticles through a lithographic process step is slightly critical,” said Sanjeev Manhas, associate professor at IIT and coauthor of the research. “Introducing the metal nanoparticles at the correct location is the main challenge, but with the state-of-the-art nanofabrication methods, it is certainly doable.”

The IIT Roorkee team and their collaborator in this research, Arvind Kumar,  a member of the technical staff at Applied Materials, introduced nanoparticles into the gate of the access transistor, which has a different work function from that of the gate electrode.  The work function difference introduces an energy valley between neighboring cells in the channel region. These valleys prevent diffusion of electrons from the aggressor cell to the victim cell, which strongly diminishes the prevalence of row hammer fail.

The researchers believe that the introduction of nanoparticles into DRAM gate stack engineering is a novel technique that could even be extended to digital logic technologies. In looking ahead to how this technique could actually become part of DRAM, the researchers have suggested possible steps whereby nanoparticles could be introduced selectively.

Kumar added: “It will require additional steps in the conventional DRAM fabrication process flow. Memory manufacturers such as Samsung, Micron, Hynix, and others may find this idea [to be] an interesting process solution for nanoparticle engineered gate stacks at a low cost.”

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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