Graphene Cages Cover Silicon Anodes for High Capacity Batteries

Graphene coating reduces cracking of silicon-based anodes in Li-ion batteries

2 min read
Graphene Cages Cover Silicon Anodes for High Capacity Batteries
Images: Hyun-Wook Lee/Stanford University

Ever since researchers first discovered that the charge life of Li-ion batteries could be improved by a factor of ten by replacing graphite on the anodes with silicon, there has been a steady stream of research aimed at making silicon actually work as an anode material in real-world batteries.

This has not been easy. The main problem has been that as they take on charge, the anodes swell enormously; when they discharge, they shrink, and the silicon cracks. Another issue has been that when lithium ions travel from anode to cathode through the electrolyte, they create a coating on the electrodes that reduces the battery’s performance.

One researcher who has been focused on developing a practical silicon-based anode is Yi Cui from both Stanford University and the Department of Energy’s SLAC National Accelerator Laboratory. Now Cui and a team of researchers from both Stanford and SLAC have developed a new approach to using silicon in the anodes of Li-ion batteries—one that might not only be technologically possible, but also commercially viable.

In research explained in the journal Nature Energy, the researchers found a way to encase each particle of silicon with a cage of graphene that enables the silicon to expand and contract without cracking. In a full-cell electrochemical test, the graphene-infused silicon anodes retained 90 percent of their charge capacity after 100 charge-discharge cycles.

While previous attempts to nanostructure silicon have managed to reduce this cracking behavior, it was by no means easy. Because it was extremely difficult to produce the nanostructured silicon, mass production was impractical at best.

In this most recent research, Cui and his colleagues simplified the manufactuing process by using larger-scale pieces of silicon that require only a relatively simple three-step process for coating them with graphene cages. The silicon used is essentially the same kind of material that is produced by milling silicon ingots to produce semiconductor chips.

The first step in the process involves coating the silicon particles with a layer of nickel. (Cui and has colleagues just reported last month on the success they had in preventing the Li-ion batteries in hover boards from exploding by coating the electrodes with a thin layer of nickel.)

However, in this latest research, the nickel coating is actually used as the surface and the catalyst for the second step: growing the graphene. The final step of the process involves using an acid on the graphene-coated silicon particles so that the nickel is etched away.

“This new method allows us to use much larger silicon particles that are one to three microns, or millionths of a meter, in diameter, which are cheap and widely available,” Cui said in a press release. “Particles this big have never performed well in battery anodes before, so this is a very exciting new achievement, and we think it offers a practical solution.”

Not only is the approach more practical from a manufacturing perspective, but it also maintains the high charge capacity of the silicon.

“Researchers have tried a number of other coatings for silicon anodes, but they all reduced the anode’s efficiency,” said Stanford postdoctoral researcher Kai Yan, in a press release. “The form-fitting graphene cages are the first coating that maintains high efficiency, and the reactions can be carried out at relatively low temperatures.”

In further research, the team will be looking to improve the process so that it can be more readily ramped up to commercial-scale production.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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