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Winner: Flat, Cheap, and Under Control

Applied Materials' new polishing technology could be the key to the coming generation of microchips

13 min read

As milestones in industrial history go, this one didn't have much in the way of spectacle. Not long ago, in a laboratory in Santa Clara, Calif., five engineers stared into a bucket of chemicals at a silicon wafer as the dull disk gradually grew shiny patches while a clunky-looking motorized polishing pad gently buffed it.

What the event lacked in pizazz it more than made up for in importance. Those little lustrous patches were the first unequivocal sign that researchers had come up with a workable means of solving one of the semiconductor industry's most pressing and intractable problems: how to manufacture faster, more powerful chips without obliterating their vanishingly fine and increasingly fragile features.

The key to meeting this challenge is an esoteric subspecialty known as wafer polishing. Integrated circuits are fabricated in layers. In addition to the few at the bottom that make up the transistors themselves, the top seven or eight of these layers are devoted to the dizzyingly complex maze of ultrafine wires that connect the chip's hundreds of millions of transistors into a functioning circuit. Basically, polishing flattens the surface of silicon wafers in between the steps that lay down the wiring layers during the chip-making process. Without such planarization, the chips would become too riddled with hills and valleys to build more than one or two layers of wiring atop their transistors, limiting the size of a circuit to just a few tens of thousands of transistors.

Mundane as it may sound, wafer polishing was a US $700 million-a-year business in 2003, according to Gartner Dataquest research. It has proved the bedrock on which, directly or indirectly, virtually every major semiconductor advance over the past quarter-century has been built. Wafer polishing has been a key enforcer for the relentless periodic doubling of IC performance known as Moore's Law; it has been a little-known player that has kept the streak going by letting technicians make wafers flat enough to support the multilayered world of wires and their increasingly delicate insulation.

It is this insulation-related challenge, in particular, that has been driving much of the work on polishing lately. Over the past two years, chip makers have been forced to begin insulating on-chip wires with new materials, notably glass doped with fluorine or carbon, and this transition has been described as one of the most difficult the semiconductor industry has ever undergone [see "Fast Films," IEEE Spectrum, February 2003]. The new polishing process developed by Applied Materials Inc., of Santa Clara, Calif., is the most extensive attempt yet to accommodate the new insulation, which is so soft that the current procedure can rip it apart. And chip making will only get more difficult: in order to make faster microprocessors, even softer insulation will have to be integrated into chips. Existing wafer-polishing techniques are simply too rough to do the job.

G. Dan Hutcheson, an industry veteran and CEO of the consulting firm VLSI Research Inc., also in Santa Clara, calls Applied's new technology a "breakthrough" and "a really big step forward." If it performs the way Applied Materials and its customers expect it to, the technology will be one of the key factors that extends Moore's Law into the realm of 4-gigabit memory chips and multibillion-transistor microprocessors.

Magnified pictures of a modern chip and of one from the late 1980s, before wafer polishing, look nothing alike [see photos, ]. The new chip has layer after layer of fine wires, or interconnects. Their edges are crisp, clean, and at right angles to one another. The older chip's features look Paleolithic by comparison—two layers of metal that follow a series of rolling hills and valleys. Wafer polishing, more than any other single process, made the difference, enabling multilayer chips that are far more complex, with interconnects fine and fast enough to shuttle bits at blazing speed.

But now, as the size of the parts that make up transistors dips down below 90 nanometers, the existing planarization process, called chemical mechanical planarization (CMP), is getting close to its limits. Invented some 15 years ago, CMP works like a woodworker's sanding block, using reactive chemicals and abrasive particles to smooth each layer of wiring on the chip. With only minor tweaks, CMP has kept pace with the demands of the ever-finer features found on microchips through half a dozen generations of integrated circuits.

The beauty of Applied Materials' new process, called electrochemical mechanical planarization, or ECMP, is that it is an extension of the existing CMP technique, replacing some of the mechanical forces at work in the polishing process with electrochemistry. The technology, which the company calls Reflexion LK Ecmp, was introduced last summer. Because it is an extension of current technology rather than a radical departure, it does not require a leap of faith on the part of chip makers, for whom a day's downtime can mean tens of millions of dollars in lost revenues. "It's not like going from horses to cars," says Hutcheson. "It's more like upgrading from a four-cylinder motor to a V-8."

To understand why Applied's new technology is critical to next-generation microcircuits, it is important to understand where its predecessor process, CMP, fits into chip fabrication and why it may not be able to do the job in the future.

Chip making begins with a smooth wafer of silicon. The electronic and physical structures that make up transistors are formed on the wafer by photolithography. In photolithography, a light-sensitive chemical called a photoresist is spread over the wafer. Laser light is then shined through a patterned mask onto the wafer. Where the light strikes the wafer, the photoresist changes chemically, or "sets." The unset resist in the pattern's shadow is etched away using chemicals, and the portions of the wafer thus exposed can be doped with ions to form transistors, coated with metal to make electrodes, or otherwise processed. Finally, the set resist is stripped away, too.

After a series of photolithography steps, the chip's devices are complete, but they must then be wired together by layers of interconnects, also constructed using photolithography. And, of course, those interconnects must be insulated from each other. That's where polishing comes in.

The CMP story begins in the late 1980s, when IBM Corp. and other chip makers ran into problems wiring together the transistors on their ICs, in those quaint times when chips had only hundreds of thousands of transistors. For previous generations of ICs, with their tens of thousands of transistors, one or two layers of wiring were all that were needed. But the new chips were packed so tightly with the tiny switches that it would take three or more layers of wiring to connect them all into useful logic circuits. Using the usual processes to lay down a layer of insulation and interconnects left behind a surface of micrometer-size ridges and valleys where the interconnects ran on the wafer surface. When technicians deposited a second layer of insulation and interconnects, it only made the wafer wavier.

After two or three layers, the surface was so bumpy, focusing a photo-lithographic pattern on it to form more interconnects was like trying to project a slide onto a crumpled newspaper. So IBM researchers came up with chemical mechanical planarization. It used a chemically reactive slurry containing abrasive particles and a round pad to grind away the bumps and ridges. Polishing left behind a flat surface that could support another layer of interconnects. Repeating CMP after adding each interconnect layer lets chip makers make eight or more levels of wiring—enough to harness together millions of transistors.

CMP also solved a second, unrelated problem, notes Liang Chen, the general manager of Applied Materials' CMP division. In the late 1990s, transistor switching speeds were at an all-time high, but the aluminum wires on ICs could not carry their signals fast enough to take advantage of them.

The speed at which a digital signal moves down a conductor on a chip is a product of how well the line conducts and how well insulated it is from other wires on the chip. By 2000, chip makers were attacking the speed problem by switching to copper from aluminum, which led to a 60 percent improvement in conductivity.

Of course, it wasn't as simple as just swapping one material for the other, and here again, polishing came to the rescue. Aluminum interconnects were fabricated by coating the wafer with a thin layer of aluminum, using photolithography and chemical etching to cut away the unwanted metal, and then filling in the gaps with an insulating material. Copper interconnects can't be formed the same way, for reasons too complex to go into here. Instead, an insulator, called a dielectric, is deposited first. Then photolithography and chemical etching carve trenches where the interconnects will go and holes for vertical layer-to-layer wiring. Finally, the wafer is dunked into a solution containing copper ions and a negative voltage is placed on the silicon wafer, causing the copper to fill in the trenches and holes.

But the process also leaves the entire wafer coated with a micrometer-thick mound of copper. CMP was the natural choice to get rid of it. But again, things were not so simple, says Chen. Electroplated copper tends to be thicker in the middle of the wafer than at the edges. Grinding the center down to spec tended to remove too much from the edges, eroding some interconnects there. The erosion increases the resistance in the wires, rendering many chips useless.

In the last couple of years, chip makers have begun tackling the slow-signal problem from the other side, by improving insulation. They began replacing the old insulating material, silicon dioxide, with new so-called low-k dielectrics. Low-k, or low-dielectric constant, films isolate interconnect lines better than the silicon dioxide they replace, allowing the wires to be more tightly packed together without the signal from one line's interfering with and slowing the signal from another.

Unfortunately, first-generation low-k materials are about four times softer than silicon dioxide. Conventional wafer polishing shreds low-k film the way steel scouring pads tear up the nonstick coating on a pan. This has made the transition to low-k one of the most difficult the semiconductor industry has ever experienced. "When I talk with chip makers," says VLSI's Hutcheson, "low-k CMP has been the number one yield problem in the fabs for the past 18 months. The low-k films are just too weak."

A year ago, Applied Materials released its first low-k polishing system, the Reflexion LK. Using three separate polishing steps, the tool removed excess copper left over from the formation of the interconnects while managing to avoid ripping up the underlying insulation. There was no magic in the technique: the polishing pad simply applied less pressure to the wafer. To grind off the excess copper on the top of the chip, the pad was pressed down fairly hard and its rotation was sped up. Once that copper was almost gone, the machine transferred the wafer to a different polishing pad with a lighter touch, about 3.5 millinewtons per square millimeter. It's about the same pressure as at the bottom of a half-full bathtub. Combined with a control system that can vary the pressure on the silicon wafer in places, Applied has had some success at flattening low-k copper wafers without losing too many chips. But few companies appear satisfied with the yields, which industry sources say typically range from 30 to 80 percent.

And for future chips, the problems will become much worse. The next two generations of chips, due out in 2007 and 2009 and comprising parts as small as 65 and 45 nm, will use even more delicate dielectrics. The only way to further improve a dielectric's insulating abilities is to add air to it in the form of pores. And porous films are far more fragile and sensitive to the pressures of polishing than anything currently in use. Today's CMP systems would tear them apart.

Electrochemical mechanical planarization

Goal: Make possible the next generations of smaller, faster, cheaper microchips

Why it's a winner: It appears capable of overcoming one of the most troubling "showstopper" problems in the semiconductor industry, thereby keeping Moore's Law on track into the next five years, at least

Organization: Applied Materials Inc.

Center of activity: Santa Clara, Calif.

Number of people on the project: More than 30

Budget: Confidential

A few years ago, Applied's Chen set out to find a way to remove excess copper from future chips without mangling the supersoft insulation beneath it. Given the significance of the problem—and the stakes riding on it—you might expect that he attacked it with a small army of scientists and engineers. Not so: he settled for a tiny platoon of just five researchers, himself included [see photo, ]. It was part of an Applied Materials initiative to use smaller groups to foster greater creativity. "A small platoon is good for innovation," says Chen. "An army is better for continuous development and improvement."

Chen encouraged his team to go off on tangents without imposing direction from above. "We argued all the time, but we all listened to every idea," says one of the five, Siew Neo.

They debated every point day and night, improvising experiments to test the latest hypothesis. As they describe the process, they sound a lot like entrepreneurs. That was just what Chen wanted: "We saw ourselves as a start-up that had to develop a technology that could attract funding from a corporation. We always asked ourselves, 'If we were a small company, would Applied Materials buy us out?' "

The first thing they needed was a basic technology to work with. At first, Chen thought it might be electropolishing, an industrial process used to smooth iron and steel [see illustration, "Winning Combination"]. Electropolishing works by passing an electrical current from a cathode through an electrolyte solution to the steel, which serves as an anode. The current causes the steel to dissolve in the electrolyte.

As a means of removing excess copper on low-k wafers, electropolishing has several positives. First, far from needing a light touch, it requires no touch at all. Second, it is very fast—an important attribute, because in IC fabrication, time really is money. Electropolishing is also very precise, removing copper at a predictable rate that depends directly on the amount of current used. Finally, it affects only the copper, leaving things like delicate dielectrics untouched.

Unfortunately, though, electropolishing a copper-coated wafer does not actually flatten the surface. Instead, it removes the copper at a uniform rate everywhere on the wafer. On a surface with uneven bulges, removing the hills digs out the valleys too.

The team spent nine months trying to get around the problem. What Chen wanted was something gentle, fast, and controllable, like electropolishing, yet capable of smoothing out a wafer, like CMP. Then the light bulb went on: why not combine processes? What if he could remove the excess copper electrochemically, but only on the hills and bulges where the polishing pad makes contact with the wafer? The copper would dissolve at a rate dependent on current rather than on how hard the polishing pad is pressed to the wafer, and, as with CMP, the wafer would be flattened. And so ECMP was born.

It took two weeks to set up the first experiment, which involved hand cranking a revolving polishing pad onto a wafer in a bucket of electrolyte. The first test yielded a dull wafer with a few shiny spots in the center. Those bright spots told them the process worked, at least in some sections, some of the time. Now the group had to find a way to achieve consistent results across the whole wafer.

They soon ditched their wobbly bucket for a wafer-processing cell that gave them precise control over positioning, polishing-pad rotation, current, and dozens of other variables. The team added engineers who began transforming the basic technology into a working tool.

So how do they dissolve the copper hills while protecting the valleys from unwanted attack? By clever engineering of the electrolyte solution.

The team's proprietary electrolyte works, they say, by forming a film over the entire copper surface that protects it from electrochemical reaction. The film, only a few molecules thick, bonds loosely to the copper. It takes only a feather-light touch of the rotating pad to rub the film off the highest spots on the wafer. The current immediately causes the exposed copper to dissolve, and the rapid flow of electrolyte over the spinning polishing pad draws the dissolved copper away from the wafer. Under the film, meanwhile, the valleys remain undisturbed.

ECMP, however, does not finish the job by itself. As the copper wears away, its resistance rises and it becomes harder to use electrochemistry to remove it. So Applied's machine uses ECMP only in the first of its three polishing stations. The other two perform the same CMP steps used in fabs now: a very low-pressure CMP polishing pad to finish off the copper and a separate pad for grinding down tantalum nitride, a barrier used to keep interconnect copper from leaching out and poisoning the chip.

So if, in the end, you have to use ordinary CMP anyway, what's so special about ECMP? Chen has a one-word answer: speed. Standard polishing systems, he says, will not be able to process next-generation chips without cracking or peeling away low-k films unless they greatly lower the amount of pressure they put on them. But in CMP the rate of copper removal is tied to how hard the wafer is pressed to the polishing pad. Using just low-pressure CMP to remove all of the copper takes far too long.

There's also another benefit: cost. "CMP is the most expensive step in chip making after lithography," says Chen. Because ECMP does most of its polishing with an inexpensive electrolyte instead of the costly slurry used now, it costs 30 percent less, he says. Dean Freeman, a principal analyst with Gartner Inc. of Stamford, Conn., agrees, noting that ordinary CMP costs about $15 to $20 per wafer, mostly for slurry. "You're knocking $4.50 to $6 off the cost of a wafer," he says. "That may not sound like much, but if you're selling processors for $1.50 each and you take 15 cents off that, it's a 10 percent improvement on your bottom line."

Given the potential of the market for polishing copper on chips—Freeman expects it nearly to quadruple to $824 million in 2009 from $225 million in 2003—Applied Materials is not the only company working on a path to the next generation of microchips. Here, Novellus Systems Inc., in San Jose, Calif., is its closest competitor, because it has already developed a process to compete with ECMP. And the competition will be fierce. "ECMP is not a compelling solution, because it only addresses one step of the process," argues Damo Srinivas, vice president and general manager of Novellus's CMP business unit. ECMP may produce a better wafer during the first step, he says, but then it introduces all the old problems when it uses conventional low-pressure polishing in the second step. "[Wafer polishing is] like when you jump off a plane without a parachute," he says. "It's only the last two inches that matter."

Chen shoots back, saying that the ECMP step makes the wafer exceptionally flat, and performing CMP on an already flat surface leads to a better finished wafer.

Naturally, Srinivas does not believe the Reflexion LK Ecmp will produce better wafers than the Novellus Xceda, his company's entry. Xceda uses abrasive-free slurries, which rely on chemistry rather than mechanical force to remove copper. "The slurry makes copper so soft, we can just rub it off with a pad without the abrasive," says Srinivas. "The beauty of it is that you can remove all the copper in a single step."

Abrasive-free slurry costs 40 percent less than conventional slurry, and Xceda can achieve economical removal rates while pressing down on the wafer with a force comparable to what Applied's polisher uses. That should be low enough, because contrary to Applied's philosophy, Srinivas expects chip makers to continue to use relatively hard insulating materials for the next two generations of chips.

Applied and Novellus will likely spend the coming years duking it out on price and performance to win sales from those top-line chip makers advancing into the cutting edge of semiconductor circuitry. But Applied remains CMP's 800-pound gorilla, and its size will likely lean many chip makers in its favor, say some analysts. For example, Gartner's Freeman sees the company's ability to integrate technology and customer service as one of its great strengths. Even though Applied entered the CMP business half a decade after its competitors, it amassed a commanding 65 percent share of the market within five years, he notes.

Despite all the promises and expectations, both Applied's and Novellus's low-k technologies are new and unproven in mass production. Still, the industry has no choice but to rely on them, just as it has relied on wafer polishing for the past decade.

To Probe Further

For background on the struggle to integrate low-k dielectrics into microchips, read Fast Films, IEEE Spectrum, February 2001. An update to the story, "SiLK Slips," appeared in the December 2003 issue.

The IEEE Electron Devices Society presents the latest in copper and low-k dielectric chip technology at the IEEE International Interconnect Technology Conference ( In 2005 it will be held 6-8 June in Burlingame, Calif.

Applied Materials Inc. and other makers of chip-processing tools often showcase their latest technology at Semicon West, a trade show next held in San Francisco 11-15 July 2005.

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