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UCLA Builds Fastest Graphene Transistor Yet

Operation at terahertz frequencies is in sight

3 min read

1 September 2010—Graphene promises to be the basis for future circuits that can operate far faster than silicon chips, but first researchers have to devise the best way to build them. The latest contender comes from the University of California, Los Angeles, where scientists and engineers have used a nanowire to build a transistor based on graphene.

The resulting field-effect transistor switches at the highest speed reported so far: 300 gigahertz in a device with a channel length (the distance between the source and the drain) of 140 nanometers. That’s roughly twice as fast as the best silicon metal-oxide-semiconductor field-effect transistor of similar proportions and comparable to transistors made of indium phosphide or gallium arsenide, which are expensive compound semiconductors.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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{"imageShortcodeIds":[]}