Electricity Makes Mortar for Nanotube Bricks

New trick links carbon nanotube arrays to boost strength and conductivity

2 min read
Electricity Makes Mortar for Nanotube Bricks
Photo: Mary Knox Merrill

Each allotrope of carbon—diamond, graphite, graphene, and fullerenes—has its unique set of interesting properties. So finding a way to get carbon to form a hybrid of these allotropes has been an enticing concept. The problem with making such hybrids is that it usually entails extreme chemical, temperature, or pressure conditions, leading to a lack of control over the final product.

Now researchers from Northeastern University, MIT, and the Korea Advanced Institute of Science and Technology (KAIST) have developed a simple, highly-scalable method for creating inter-allotropic transformations and hybridizations of carbon that appear across large-area ​carbon networks. Using alternating pulses of electricity across single-walled carbon nanotubes (SWNTs) they transform them into larger-diameter SWNTs, multi-walled CNTs of varying morphologies, or multi-layered graphene nanoribbons. They reported the details in  the journal Nature Communications.

The key feature of the method is that it produces molecular junctions for the carbon nanotubes that have superior electrical and thermal conductivity compared to carbon nanotubes arrays that are junction-free.

To visualize the difference between a CNT array with molecular junctions and one without, the researchers say that the one without is like a wall of bricks without mortar, while the one with molecular junctions is like a brick wall made using mortar.

“We have filled in the gaps with cement,” said co-​​author Swastik Kar, an assistant pro­fessor of physics at Northeastern, in the press release. “We started with single-​​walled carbon nanotubes,” he added, “and then used this pioneering method to bring them together.”

The researchers believe that CNT arrays using these junctions could be useful for reinforcing composite materials. In the last few years, we have begun to see the use of CNTs in composites that actually improve the strength of the composite as opposed to just replacing a regular resin material. (In research back in 2012, scientists in Switzerland demonstrated how using magnetic forces could orient the carbon nanotubes in the composite to impart even greater strength.)

While stronger composites are indeed an attractive characteristic for these new CNT arrays, their improved electrical and thermal conductivity properties should be attractive for electronic applications as well.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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