In the past decade, many technologists have adopted the mantra that software is eating the world. However, all of that software has to run on something. And that something is silicon.
Unfortunately, the chip world has hit a roadblock with the fade-out of Moore's Law.
The challenge of building circuits that require years of research and development, combined with rapid advancements in software, is making it more difficult for silicon designers to predict the future. Given the multimillion-dollar stakes associated with new chip architectures, every investment is a big risk.
Meanwhile, Apple, Facebook, Google, and Samsung have decided to build their own silicon instead of relying on Intel, Qualcomm, or others. Thus, investing hundreds of millions of dollars into a new chip architecture becomes even riskier, with less potential to win a major new customer.
These shifts have produced a boom of interest in a chip architecture called RISC-V (pronounced “risk-five"), which was created eight years ago at the University of California, Berkeley. RISC-V is the fifth generation of the “reduced instruction set computer" type of architecture. Just like the instruction sets for the ARM, PowerPC, or x86 architectures, RISC-V defines how the computer operates at the most basic software level.
But what's so compelling about RISC-V isn't the technology—it's the economics. The instruction set is open source. Anyone can download it and design a chip based on the architecture without paying a fee. If you wanted to do that with ARM, you'd have to pay its developer, Arm Holding, a few million dollars for a license. If you wanted to use x86, you're out of luck because Intel licenses its instruction set only to Advanced Micro Devices.
For manufacturers, the open-source approach could lower the risks associated with building custom chips. Already, Nvidia and Western Digital Corp. have decided to use RISC-V in their own internally developed silicon. Western Digital's chief technology officer has said that in 2019 or 2020, the company will unveil a new RISC-V processor for the more than 1 billion cores the storage firm ships each year. Likewise, Nvidia is using RISC-V for a governing microcontroller that it places on the board to manage its massively multicore graphics processors.
For years, giant tech firms have designed their own silicon to handle special jobs associated with their equipment. With RISC-V, a tech firm can now start with an instruction set and then invest in CPU architects and other engineers to build out and test chips without paying a huge up-front licensing fee.
For example, a startup in France called GreenWaves Technologies has built a dedicated chip for the Internet of Things. The company chose the RISC-V architecture because it wanted to avoid raising the crazy amounts of money typically needed for chip startups. GreenWaves CEO Loic Lietar said the company has raised €3.1 million (US $3.6 million) and has already managed to produce a sample of its silicon.
This technology lowers the cost of creating custom chips, which means more and more companies may elect to build their own. As for the existing players, I don't think RISC-V represents a bigger threat to Intel than does the slow fade of Moore's Law and former customers deciding to build their own dedicated silicon. And I don't think Arm will necessarily lose licensing fees to RISC-V right away—but the technology could bring on a wave of competitive silicon that hurts incumbents in the long run.
This article appears in the August 2018 print issue as “The Rise of RISC."
Stacey Higginbotham writes “Internet of Everything,” Spectrum’s column about how connected devices shape our lives. Tech writer Higginbotham enjoys covering the Internet of Things because the topic encompasses semiconductors, wireless networks, and computing hardware. She alsopublishes a weekly newsletter called Stacey Knows Things and hosts The Internet of Things Podcast. Higginbotham figures she has at least 60 IoT gadgets in her Austin, Texas, home, and she admits, “Frankly, I hate keeping it all up and running.”