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Engineering jobs will soon be on offer at a factory that will produce energy-saving color displays at the site of the Hsinshu Science Park in northern Taiwan. Qualcomm and Taiwan’s Ministry of Economic Affairs reported on 3 January that the chipmaker, based in San Francisco, is investing US $1 billion to build the factory, which will turn out small color displays for a new generation of e-readers and smartphones with built-in e-reader capability that use Qualcomm’s Mirasol technology. The technology is meant to extend battery life by making the screen readable without a backlight. (It takes its name from the words “mira” and “sol,” which literally mean “look” and “sun.”) According to the Taiwanese government, Qualcomm has reserved a seven-hectare lot upon which the plant will be erected. Press releases announcing the Qualcomm investment noted that it will help a Taiwanese chipmaking industry beset by competition from its Asian rivals. There has been no word on the high-dollar investments the U.S. based chipmaker plans to make in order to aid the U.S. economy.

 

Photo: Taiwan Semiconductor Manufacturing Co., Ltd.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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