15 June 2010—A test circuit built with nanowires of silicon could point the way to much smaller transistors, say the IBM researchers who created it.
Researchers from IBM’s Thomas J. Watson Research Center announced today at the annual Symposium on VLSI Technology, in Honolulu, that they have built a ring oscillator out of field-effect transistors (FETs) based on nanowires with diameters as small as 3 nanometers. The oscillator—is composed of 25 inverters using negative- and positive-channel FETs.
The device, which demonstrated a delay of just 10 picoseconds per stage, shows that engineers can build a working circuit from transistors with much shorter channel lengths than today’s devices. Current flows through an FET’s channel under the control of the device’s gate. Scaling down the channel length will be critical if the dimensions of circuits on silicon chips are to continue to shrink, says Jeffrey Sleight, a senior technical staff member at IBM.
As the channels in the FETs get shorter, the dielectric material that separates the gate from the channel must get thinner. But the thinner the gate dielectric is, the more current leaks through, until eventually there’s so much current flowing that the circuit won’t turn off. With no on-off capacity, there’s no digital logic.
Sleight says that circuits still work well with today’s gate lengths of roughly 35 to 40 nm but won’t in the future. “If you want to go much further, to extend to gates in the 15- to 20-nm range, it becomes pretty hard to conceive how to do that using normal, planar devices,” he says.
His group’s solution is to build “gate all around” transistors, in which silicon nanowires are surrounded on all sides by the gate dielectric. Today’s planar transistors have the gate on top of the silicon. Sleight says their design is like having a gate on the top, bottom, right, and left sides—although the silicon in this case is actually cylindrical. “Having the additional gating gives you better channel control,” he says.
To make such a design work, he points out, it’s generally accepted that the silicon nanowires must be less than 10 nm thick. IBM’s process let them build nanowires as small as 3 nm in diameter. The technique is very similar to standard complementary metal-oxide semiconductor (CMOS) processing, Sleight says. The team started with a layer of silicon atop a layer of silicon dioxide and used lithography to etch the right shape in the silicon. The researchers then removed the oxide from underneath, leaving suspended horizontal silicon wires. They annealed the silicon by heating it in a hydrogen atmosphere, thus making the wires smoother.
An advantage of nanowire FET design is that unlike planar design, it doesn’t require doping the silicon with other materials to control its electrical behavior. That’s fine for today’s transistors, but in arrays of devices with features smaller than 22 nm, it’s hard to control the concentration of dopants. The resulting variations can affect the voltage at which each device turns on. In the nanowire FET configuration, the surrounding gate provides the control the dopants ordinarily would, so they’re just not necessary.
At last year’s VLSI Symposium, a team from Samsung Electronics reported having made gate-all-around silicon nanowire FETs, but their nanowires, at 13 nm, were thicker. Sleight says that he and his IBM colleagues not only reduced the size of the nanowires and improved the performance of the individual FETs, they went further by building an actual circuit: the ring oscillator.
Ming Li, one of the Samsung nanowire researchers, calls the IBM work “interesting,” saying, “It did make an effective ring oscillator with a quite realistic process control.” Li adds that getting the right balance of different electrical characteristics in the device will be key to someday moving it out of the lab.
Sleight says it will be several years before this type of circuit could actually be used in chips.