IBM Engineers Make Recipe for 22-Nanometer Transistors

Mix of metals and dielectrics lets them shrink transistors and maintain performance at the same time

2 min read

Samuel K. Moore is IEEE Spectrum’s semiconductor editor.

15 June 2009—Engineers at IBM reported this week at the VLSI Symposia that they have come up with a transistor design that will carry the company through to the 22-nanometer generation of chips—two generations beyond what the company is pushing into production this year. The design is a modification of the metals and insulation in the gate stack, the part of the transistor that controls the flow of electricity through it. Other firms, such as Intel, have changed their gate-stack construction in recent years to include so-called high- k dielectrics and metal gates, but IBM claims that its technique is the first to control two crucial electronic parameters at once.

Typically, research efforts to make 22-nm transistors have focused either on making the gate dielectric more permeable to an electric field, scaling down its ”equivalent oxide thickness,” or they’ve focused on lowering the device’s threshold voltage, the amount of voltage needed at the transistor’s gate to turn the transistor on. Threshold voltage must be made low, around 0.1 to 0.2 volts, in order to get a suitable amount of current flowing through the transistor during its normal operation.

”Getting low-threshold voltage is the holy grail for CMOS [complementary metal-oxide semiconductors], but it needs to be done at extreme scaling,” says Vijay Narayanan, manager of IBM’s high- k /metal-gate process development. ”People tend to do one, but not both at the same time.”

CMOS circuits are composed of transistors with a negatively doped channel (nFET) and those with a positively doped channel (pFET). It’s the pFET that has been the biggest problem. Oxygen that comes from a thin veneer of silicon dioxide between the gate stack and the silicon substrate makes it hard to improve both threshold voltage and equivalent oxide thickness of pFETs, but the IBM researchers used a metal in the gate that soaked up the oxygen.

Narayanan adds that the technology is compatible with the company’s existing high- k /metal-gate process, which involves constructing the gate stack first and then building the rest of the transistor around it. (Intel uses the opposite scheme, building the gate stack last.)

”Essentially, this enables IBM to be a leader in high-performance chips for the server market and in high-performance gaming chips,” says Narayanan. IBM held 32 percent of the server market in 2008, according to market research firm IDC. All three major game consoles—Microsoft’s Xbox 360, Sony’s PlayStation 3, and Nintendo’s Wii—rely on IBM processors. In addition, the transistor design’s low-current leakage will be important to the company’s foundry customers who are looking for low-power chips, says Narayanan.

Intel shot ahead of its rivals in late 2007 when it started manufacturing its 45-nm generation of chips, the first to include high- k dielectrics and metal gates. IBM’s 45-nm chips, which are in production now, use an extension of the conventional gate-stack technology but on a different kind of wafer, silicon-on-insulator. Narayanan says that the right technology node for the introduction of high- k metal-gate technology is 32 nm, a manufacturing process IBM has under development now.

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