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Graphene-Girded Interconnects Could Enable Next-Gen Chips

Current in next-generation chips could literally blow copper interconnects away, but graphene can keep them together

2 min read
to the left, a blown-out copper interconnect, to the right, a graphene-girded interconnect
Image: Stanford University

Most of the celebration and hand wringing over Moore’s law focuses on the ever-shrinking silicon transistor. But increasingly researchers are focusing on another critical part of the infrastructure: the copper wires that connect individual transistors into complex circuits.

At the IEEE International Electron Devices Meeting in San Francisco in December, researchers described the coming problems for copper interconnects, and debated ways of getting around them. One approach studied by a group led by Stanford electrical engineer H.-S. Philip Wong, is to bolster copper with graphene. Wong’s group found that the nanomaterial can alleviate a major problem facing copper, called electron migration.

Copper wires are getting so thin, and must carry so much current, that the atoms in the wire can literally get blown out of place. “The electron wind can physically move the copper atoms and create a void,” says Wong. Growing graphene around copper wires prevents this, according to research Wong’s group presented at the meeting. It also seems to bring down the resistance of the copper wires.

Ruth Brain, an Intel Fellow and director of interconnect technology and integration at the company’s Hillsboro, Ore. location, explained how interconnects are being pushed to their limits. More transistors per chip area means more interconnects have been installed to connect them. The first chips to use copper interconnects, which were adopted in 2000, had 1 kilometer of the wiring per square centimeter. Today’s 14-nanometer node processors contain more than 10 kilometers of copper wiring in the same area, she said.

In order to improve performance, the ever-narrowing copper wires must carry ever more current. The amount of current per area in a wire is called its current density, which has been increasing on cutting-edge chips for two reasons: Wires are shrinking and higher currents must course through them to enable the faster switching speeds that boost performance. 

And herein lies the challenge. The narrower the wire, the higher its resistance. “Interconnects have had to shrink while increasing the current densities by 20 times,” said Brain. “You would burn your house down if you did this in your house.”

Today’s solution is to deposit copper interconnects within trenches lined with 2-nanometer-thick walls of tantalum nitride. This lining keeps copper from escaping, and Wong says copper will probably endure through the coming 10- and the 7-nm nodes. As device features keep shrinking, though, 2-nm walls will be far too thick, says Wong. Researchers are investigating other electromigration-preventing linings including ruthenium and magnesium, but at 0.3 nm, he says, nothing can be thinner than graphene.

The semiconductor industry avoids integrating new materials as long as possible, but Wong says there isn’t much choice in this situation: If copper’s life can’t be extended, it will have to be replaced with a new material, such as cobalt, anyway.

The Stanford group worked with Lam Research, which makes chip manufacturing tools, as well as researchers from Zhejiang University, in China, to make and test the composite interconnects. The materials are a good pair: graphene is often made by growing it on copper. Lam Research has developed a proprietary process for doing this at temperatures that won’t damage the rest of the chip—below 400 °C. Compared to copper alone, the composite improved electromigration by a factor of 10. And the composite wires had half the electrical resistance.

Wong says the interconnect problem can no longer be dismissed. “Before, most of the time we were hearing about transistors,” he says. “Now it’s not just transistors but wires, memory—many other things that were previously not a problem are beginning to be a problem.”

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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