Foundries Rush 3-D Transistors

Nearly two years after Intel, the world's leading foundries scramble to get FinFETs into the hands of chip designers

3 min read
Foundries Rush 3-D Transistors

The 3-D transistor is poised to go mainstream. After falling behind Intel, the world’s biggest foundries are all gearing up to produce these cutting edge switches. And to accelerate the process, some have opted to take an unusual step: marrying the new transistors with an older approach to building the wiring that ties them together on a chip.

The hope is that this hybrid strategy will help foundries make 3-D transistors, or FinFETs, available to most of the world’s semiconductor firms by 2014, a good year earlier than anticipated. That could help close the gap with Intel, which unveiled the first commercial 3-D transistor process in 2011 and likely aims to supply the technology, with few exceptions, only to itself. Intel plans to release the transistors in smartphone and tablet chips tailor-made to compete against the foundries’ customers. 

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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