Here’s something you don’t see very often at government-sponsored technology meetings—spontaneous applause. It happened at DARPA’s Electronics Resurgence Initiative Summit this week when MIT assistant professor Max Shulaker held up a silicon wafer that is the first step in proving DARPA’s plan to turn a trailing edge foundry into something that can produce chips that can compete—even in a limited sense—with the world’s leading edge foundries.
“This wafer was made just last Friday… and it’s the first monolithic 3D IC ever fabricated within a foundry,” he told the crowd of several hundred engineers Tuesday in Detroit. On the wafer were multiple chips made of a layer of CMOS carbon nanotube transistors and a layer of RRAM memory cells built atop one another and linked together vertically with a dense array of connectors called vias. The idea behind the DARPA-funded project, called 3DSoC, is that chips made with multiple layers of both would have a 50-fold performance advantage over today’s 7-nanometer chips. That’s especially ambitious given that the lithographic process the new chips are based on (the 90-nanometer node) was last cutting-edge back in 2004.
The project is only about a year old, but by the end of its 3.5-year run, DARPA wants a foundry technology that makes chips with 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between the layers that can transmit 50 terabits per second while consuming less than 2 picojoules per bit.
What Shulaker showed on Tuesday can’t do all that yet, of course. But it’s a key milestone in that journey. Together with SkyWater Technology Foundry and other partners “we’ve completely reinvented how we manufacture this technology, transforming it from a technology that only worked in our academic labs to a technology that can and is already today working inside a commercial fabrication facility within a U.S. foundry,” he said.
Key to the technology’s potential advantage over today’s 2-D silicon is the ability to stack multiple layers of CMOS logic and nonvolatile memory while linking those layers—the 3DSoC team calls them “tiers”—with vertical connections that are orders of magnitude more narrow and densely-packed than any other 3-D technology can offer.
Such a technology can’t be achieved in silicon, because the temperatures needed to construct a layer of silicon logic—up to 1,000 degrees C—are high enough to destroy the layer beneath it. The 3DSoC tech uses carbon nanotube-based transistors instead, which can be built at temperatures below 450 degrees C. Likewise, the RRAM tiers are also built with a low temperature process. So multiple layers can be constructed without doing injury to the tiers beneath.
How did the 3DSoC team go from laboratory curiosity to commercial process? “It was a stepwise approach,” SkyWater CTO Brad Ferguson told IEEE Spectrum later that day. For example, they figured out the process for NMOS carbon nanotube transistors and PMOS transistors separately, and built separate wafers of each before making any wafers that combined them into CMOS circuits. They fabricated wafers of RRAM separately as well, and then figured out to make vertical connections to that tier. “The stepwise approach really burned down a lot of the risks … along the way we did a lot of learning.”
The next major milestone is to integrate two layers each of nanotube transistors RRAM by the end of the year, says Ferguson. For the phase following that, SkyWater and the rest of the team will be working on improving yield. “We’re achieving economically viable bit yield [for RRAM] at this point,” he says. “For the first run, that’s pretty darn good.”
In the final phase, partners and potential customers will use the process design kit, the first version of which is now complete, to get prototype chips made. From there, SkyWater will be able to build a business around the process and license the technology to other foundries.
What’s potentially just as exciting is that the performance gains could continue to improve. The process could be upgraded to work at 65 nanometers or even more advanced manufacturing nodes, leading to higher densities and faster, more powerful systems. “Once 3D SoC is implemented at the relaxed mature 90-nm node, we have decades-worth of [innovation] to be had relying on conventional techniques,” said Shulaker.
That would put SkyWater on a different playing field. “It perhaps makes us relevant to customers that need the bleeding edge, like Qualcomm,” said Ferguson, referring to statements made earlier that day by Qualcomm CEO Steve Mollenkopf. “They say they have to be at the leading edge. Now we, [a 90-nanometer foundry], could potentially be relevant to them.”