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EUV Lithography Finally Ready for Chip Manufacturing

This long-awaited technology will extend the life of Moore’s Law

6 min read
Photo: IMEC
Silicon Savior: ASML’s extreme ultraviolet lithography machines are being installed all over the world in preparation for the technology’s long-awaited debut in chipmaking.
Photo: IMEC

“A fab is like an iceberg,” someone tells me. I can’t tell who because we’re all covered head to toe in clean-room garb. A tour of GlobalFoundriesFab 8 in Malta, N.Y., certainly reinforces that analogy: We’ve just come up from the “sub-fab,” the 10 meters of vertical space under the floor, where pipes and wires snake down from each semiconductor-manufacturing tool above to a set of automated chemical handlers, water analyzers, power conditioners, and—in the case of the unit I’ve come to see—kilowatt-class lasers.

The laser system takes up 15 to 20 square meters out of perhaps 80 square meters of the floor space required for a single machine. About halfway through a six-week assembly process of mind-bending complexity, the equipment making up the tip of the iceberg is a house-size agglomeration of shiny metal tubes, opaque chambers, and wiring. A half dozen bunny-suited technicians are moving around the behemoth, probing and connecting things in a carefully choreographed procedure.

The giant machine garnering all this attention is an extreme ultraviolet lithography tool. For more than a decade, the semiconductor-manufacturing industry has been alternately hoping EUV can save Moore’s Law and despairing that the technology will never arrive. But it’s finally here, and none too soon.

Samsung was the first to claim it will be ready to produce chips for customers using EUV tools, saying that will happen in the second half of 2018. But its competitors GlobalFoundries, Taiwan Semiconductor Manufacturing Co. (TSMC), and Intel are clearly on track to do the same within a quarter or two.

Intel won’t reveal anything about its road map, saying through a spokesperson, “We are committed to bringing EUV into production as soon as the technology is ready at an effective cost.” But VLSI Research analyst G. Dan Hutcheson points out that Intel has purchased more EUV tools than any other company.

GlobalFoundries, Samsung, and TSMC have been more forthcoming, and they seem to be following the same playbook. They are each introducing EUV in a second iteration of a 7-nanometer manufacturing process—the 7-nm node, as it’s called—which they will have run for as long as a year using the pre-EUV technology.

The thinking is clearly that two big changes would be too much to handle. Gary Patton, GlobalFoundries’ chief technology officer, describes the 7-nm process even without EUV as “an extreme sport.” If things work out and foundries can keep the tool running 80 percent of the time or more—which both GlobalFoundries and TSMC say they can do—EUV will actually make the 7-nm process simpler and cheaper. To understand why, though, you have to have a good grasp of how chipmaking is done now.

“Lithography is the heart of the fab,” says Thomas Caulfield, senior vice president and general manager of GlobalFoundries’ Fab 8. Silicon wafers have to make many stops along the way in their transformation from smooth blanks to iridescent platters jam-packed with 13-billion-transistor microprocessors. And many of those stops take place inside a photolithography tool.

Today’s state-of-the-art process is called 193-nm immersion lithography. As the name implies, light with a wavelength of 193 nm shines through a patterned surface called a photomask. That process casts the pattern through water onto the silicon wafer, where it is fixed by a photosensitive chemical and then etched onto the wafer. The problem is that light can’t directly define features smaller than its own wavelength. And 193 nm is so much longer than the size of the features modern chips need. These days it takes a host of optical tricks and work-arounds to make up the difference. The most costly of these is the use of as many as three or four different photomasks to produce a single pattern on a chip. With today’s most complex processors, that means a wafer could need some 80 trips though the lithography tool.

EUV lithography’s reason for being is that it uses 13.5-nm light, which is much closer to the size of the final features to be printed. With it, manufacturers can turn three or four lithography steps into one. For its 7-nm EUV process, GlobalFoundries will replace 15 steps with just 5. John Lin, TSMC’s director of litho equipment and mask technology, says his company plans a similar reduction.

While that will make the work at 7 nm faster and cheaper, it’s the nodes beyond where EUV will be absolutely crucial. “If you didn’t use EUV for 5 nm, it’d be more than 100 [lithographic steps],” says Patton. “That’d be insane.”

Patton makes it sound as though EUV lithography arrived just in time, and in a way it has. But it has been a decades-long journey with many moments when one expert or another declared it dead. Its arrival in production now still seems a bit unbelievable to some observers.

According to VLSI’s Hutcheson, the long delay shouldn’t be that surprising. “Core technology takes a lot longer than anyone would expect,” he says. Despite using different light sources along the way, lithography hasn’t really had a change in technology this fundamental since the 1980s, he argues.

Throughout most of EUV’s history, the main problem has been the light source, and considering its complexity, that’s not surprising. In a vacuum chamber at one end of the machine, microscopic droplets of molten tin are fired in a stream as two laser blasts strike each of them sequentially. The first one hits the droplets so precisely that they flatten into misty discs. The second blasts them with so much power that they become little balls of plasma shining with EUV light.

Light-source developers couldn’t provide the needed power for years, and they consistently overpromised and underdelivered. But now concerns about the light source have basically been put to rest. One source capable of outputting 205 watts of light is ready to ship, and ASML has demonstrated 250 W in the lab. “We are confident that ASML will achieve 250 W in the field in 2018,” says TSMC’s Lin.

Even though most of the light is lost on its multireflector trip through the machine, that wattage will work even for the 5 nm node. But for 3 nm, analysts think that chipmakers will need 500 W, and maybe 1,000 W a couple generations further on for 1 nm. The former is doable through a combination of increasing the power of the drive lasers, improved efficiency at converting the laser energy to EUV light, and more precise stability and control. But the latter would require an absurd amount of power. The EUV tool and its associated drive lasers and other equipment I saw at GlobalFoundries draw about 1 megawatt to ultimately deliver just a few tens of watts of light power to the wafer. Caulfield tells me they had to add 10 percent to Fab 8’s power supply to accommodate the two EUV tools being installed for 2018.

Although the power challenge has now been largely overcome, that’s not to say that EUV lithography is working perfectly. There are still some problems with the masks. These EUV masks are quite different from those used for 193-nm lithography in that they reflect light—using dozens of nanoscale layers composed of different materials—instead of transmitting it. In practice they have imperfections, ones that are hard to spot and avoid. Also, the transparent covers—called pellicles—that usually protect lithography masks from dust are not fully ready for EUV.

Pellicles are important because, even within the ultraclean environment inside the EUV machine—which itself is in a top-of-the-line clean room—some dust is still generated in the manufacturing process. A speck falling onto the photomask can cast a device-killing shadow on every single finished chip and render a rather expensive mask worthless.

That’s why in today’s lithography tools, the photomask is covered by a transparent pellicle. Think of it as safety glasses for the mask. But today’s pellicles are opaque to EUV.

To work for EUV, pellicles must have extrathin membranes to make them transparent, but they must be strong enough to withstand mechanical shocks from the normal scanning movement of the photomask and the thermal shocks that come with blasts of energetic EUV radiation.

Even without a good enough pellicle in hand, chipmakers are gambling that with only a few EUV steps in the process, the risk of using a naked mask will be worth it. That work-around can’t continue once chipmakers start relying on EUV for more steps, but solutions are in the works. ASML, for one, has tested a design for use with a 250-W EUV light source. “The design for pellicles has to evolve,” says Vivek Bakshi, an EUV consultant. “I don’t see it as a showstopper.”

The more serious problem is that there’s still no good way to inspect a photomask for defects. Ideally, you’d want to use EUV light to scan for spots that need repair. But that technology, called actinic patterned-mask inspection, is still in the works. All chipmakers have right now is a handful of stopgap measures. One is to use existing tools that rely on 193-nm light. But at the 7-nm technology node, using such an outsize wavelength is like trying to read braille with your elbow: It kind of works, but you’ll probably miss something. Electron-beam inspection tools have the resolution but can be slow. ASML shipped its first electron-beam inspection tool recently.

Chipmakers can also use what they call a “print check.” That is, they stick the mask in the EUV lithography tool, producing a patterned silicon wafer, and inspect that wafer itself, a more time-consuming and expensive process than they’d like.

Nevertheless, chipmakers are moving ahead. “People adopting EUV are defining its use, so that these things don’t get in the way,” says Aki Fujimura, CEO of electron-beam technology firm D2S and an expert in the technology used to write patterns on photomasks.

Technology experts expect that some very clever engineers will soon solve this and other remaining problems of EUV lithography. Indeed, the different chipmakers will probably distinguish themselves by how well they can find engineers who are up to the task. “We spend all this money on the tools, but if we don’t have the right people, we can’t do this,” says Patton.

This article appears in the January 2018 print magazine as “EUV Lithography Finally Ready for Fabs.”

This article was corrected on 11 January to properly characterize Samsung’s mask tools.

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