DARPA Picks Its First Set of Winners in Electronics Resurgence Initiative

Teams announced in design, architecture, and materials and integration programs under the $1.5 billion effort to remake U.S. electronics

7 min read

Samuel K. Moore is IEEE Spectrum’s semiconductor editor.

Illustration of a dollar sign on a circuit board
Illustration: iStockphoto

Hundreds of engineers gathered at the DARPA Electronics Resurgence Initiative Summit in San Francisco yesterday to hear that dozens of them were getting millions (one group was awarded more than US $60 million) to tackle some big questions. If researchers can answer them in the affirmative, they will keep electronics going long after Moore’s Law is a thing of the past. And in the process they’ll likely change the nature of the industry as well as the jobs of engineers.

The Electronics Resurgence Initiative has three main thrusts: design, architecture, and materials and integration. (For a deep dive into the programs and the reasoning behind them, see last week’s interview with the initiative’s leader, Bill Chappell.)

In the design field, DARPA’s Microsystems Technology Office deputy director, Jay Lewis, announced the funding for projects under two efforts, IDEA and POSH. The two programs seek to usher in an era of the 24-hour design cycle for defense-related hardware systems, shorten the time it takes to upgrade hardware, and enable the proliferation of custom systems-on-chip.

IDEA aims to create a “no human in the loop” layout generator that would enable users with even limited electronic design expertise to complete the physical design of electronic hardware within 24 hours. The biggest award in that sector ($24.1 million) went to a group led by David White at the electronic design automation firm Cadence, but including several partners. “This program will set the stage for enhancing the entire span of our analog, digital, verification, package and PCB EDA technologies, providing our customers with the most advanced system design enablement solutions,” said Anirudh Devgan, president of Cadence, in a statement. In an address at the Summit, Cadence senior vice president Tom Beckley pointed out that the company’s premier EDA platform, Virtuoso, already includes machine-learning technology, and they have about 30 engineers working on machine learning. The IDEA project will help them add to that number.

PrincipalFunds (millions of US$)InstitutionsDescription
David White24.1Cadence, Nvidia, University of California Berkeley, Univeristy of Texas Austin, Carnegie Mellon UniversityA no-human-in-the-loop layout generator for analog-, package-, and board design
Andrew Kahng11.3University of California, San Diego; Qualcomm, ARM, University of Minnesota, Brown University, University of Michigan, Univerisity of Illinois Urbana-Champaign; University of Texas, DallasOpen source layout generator for digital circuits, packages, and boards through the use of extreme partitioning, cloud computing, and machine learning
Jonathan Bachrach8.7Northrop Grumman, JITXAn open source system generator, open parts data base, and circuit optimizer to enable automatic design of boards and packages baseed on user design intent
David Wentloff6.4University of Michigan, ARM, Univeristy of Virgina.Automated SoC synthesis tool for both analog and digital components from a user-intent-based description
Sachin Sapatnekar5.3University of Minnesota, Intel, Texas A&MOpen source layout generator for analog circuits throgh the use of template-drive designs and machine learning
David Wentzlaff2.8Princeton University, University of WashingtonDevelop open-source high-imapct digital cicuit, analgo circuit, board, and package validation test cases and evaluate the IDEA design flow
Martin Wong1.7University of IllinoisOpen source massively parallel EDA infrastructure and stati timing analysis engine
Nan Sun1.7University of TexasMachine learning-based software for analog layout constraint generation, placement, and routing that leverages human-expert constraints derived from existing analog layouts
Dan Jiao1.3Purdue UniversityFirst principle physics-based extraction flow for PCBs, packages, and System-on-Chips
Rajit Manohar1.2Yale University, UC Berkeley, UT Austin, Sandia National LabsDevelop an open-source EDA flow for asynchronous circuits
Pierre-Emmanuel Gaillardon1Univeristy of UtahOpen source logic sysnthesis leveraging logic optimization engines and machine-learning-based logic synthesis technqiues based on input circuit topology

The othe design effort, POSH (for Posh Open Source Hardware) aims to bring the culture and capability of open source to hardware design. “To help democratize access to custom, high-performance SoCs, the POSH program seeks to develop a sustainable ecosystem of open-source IP and accompanying validation tools,” said Andreas Olofsson, the program manager leading IDEA and POSH, in a statement. “Through POSH, we hope to eliminate the need to start from scratch with every new design, creating a verified foundation to build from while providing deeper assurance to users based on the open source inspection process.”

PrincipalFunds (millions of US$)InstitutionsDescription
Eric Keiter6.9Sandia National Labs, Yale University, University of California BerkeleyMassively parallel distributed open source simulation tools
Alex Rabinovitch6.1Synopsys, Lockheed Martin, Analog Devices, Analog Circuit WorksAn emulation platform for high-performance analog mixed signal functional verification with transistor-level accuracy
Tony Levi6University of Southern California, GlobalFoundriesHigh-performance open-source analog circuits
Clark Barrett5.9Stanford University, Princeton UniversityOpen source model checkers and instruction-level abstractions for arbitraray hardware and mixed-signal models for formal verification of analog IP blocks
Michael Taylor2.7Univeristy of Washington, Boston UniversityHigh-performance open source 64-bit RISC-V multicore processor
Richard C.J. Shi2.5University of WashingtonPDK-independent topology description language for the deliveriy of open source mixed signal IP modules portable from 180-nm to 14-nm technology nodes
David Wentzlaff1.8Princeton University, Cornell UniversityOpen-source FPGA fabric and scalable coherence memory system for creation of an open source hardware ecosystem
Edgar Inglesias1.2Xilinx, GreenSoCs, FEIMTECH ABAn open source appraoch for fast mixed-accuracy cosimulation that allows hardware and software to be co-developed, debugged, and verified
Pierre-Emmanuel Gaillardon0.9Univeristy of UtahOpen-source FPGA generation framework
Sheief Reda0.6Brown UniversityOpen-source circuits and software for thermal-, voltage-, and prcoess sensors, employing an exploratory solver based on distributed set of die sensors
Chinh Le0.6LeWiz CommunicationsHigh-quality open-source implementations of Ethernet controllers

In its architecture efforts, DARPA is aiming for a future where systems-on-chips contain a lot of specialized hardware—such as accelerators hardwired to do particular functions fast—instead of focusing on generalized computing. Software for these chips must still be easy to write and yet be able to take the best advantage of the accelerators involved. [For more, see last week's interview with Chappell.] The two newly funded programs under the architecture effort are called Software Defined Hardware (SDH) and Domain-Specific System on Chip (DSSoC).

According to DARPA, the SDH program aims to develop hardware and software that can be reconfigured in real time based on the sort of data being processed, adapting the computing architecture for the workload in milliseconds. Here, the big winner was a $22.7 million project headed by Stephen Keckler at Nvidia but also including researchers from MIT, the University of Illinois Urbana-Champaign, and the University of California Davis.

PrincipalFunds (millions of US$)InstitutionsDescription
Stephen Keckler22.7Nvidia, MIT, University of Illinois Urbana-Champaign, University of California DavisReconfigurable compute arrays with explicit data orchestration
Michael Bedford Taylor9University of Washington, Cornell University, Dini Group, XilinxPolymorphic hybrid ASIC/FPGA architectures
Ron Dreslinski9University of Michigan, ARM, Arizona State University, University of EdinburghFast, low energy interconnect for reconfigurable compute arrays
Kunle Olukotun8Stanford University, SambaNova SystemsHybrid configurable arrays coupled with on-the-fly compiler optimization
Margaret Martonosi5.8Princeton University, Columbia UniversitySpecialized and decoupled data compute and data supply programming for malleable tile-based computation
Brad Gaynor5.5Systems & Technology Research, Northeaster University, Purdue UniversityData dependent Just-in-Time hardware/software 
Joshua Fryman4.5IntelHigh-throughput compute near memory and interconnect networks
vivek Sarkar4.5Georgia Tech, Univeristy of Illinois Urbana-Champaign, University of Michigan, University of Southern CaliforniaAutomatically discover and generate parameterized kernels for hardware and software co-optimization
Shekhar Borkar2QualcommDynamically optimizable data path for multi-core systems

The DSSoC arm of the architecture effort is somewhat smaller but is still funding two groups at more than $10 million each. “It is critical for the DoD to have flexible, adaptable radio systems that are capable of managing and combating a complex signal environment,” Tom Rondeau, the program manager leading DSSoC said in a press release. “These devices must be programmable like general purpose processors, but also capable of crunching a lot of math with low power.”

PrincipalFunds (millions of US$)InstitutionsDescription
Daniel Bliss17.4Arizona State University, University of Michigan, University of Arizona, Carnegie Mellon, General Dynamics, ARM, EpiSySHeterogeneous processors with specialization to support multifunction RF systems that require dramatically increased processing flexibility at low power
Pradip Bose14.7IBM, Columbia, Harvard, University of Illinois at Urbana-ChampaignQuickly design and implement an easily programmed domain-specific SoC for real-time cognitive decision engines within smart connected vehicles
Mark Horowitz6.4Stanford University, SambaNova SystemsVisual computing program will use agile design techniques to enable application experts to develop ideas quickly for an optimized SoC for visual computing
Dr. Jeffrey Vetter6Oak Ridge National LabNew tools for performance modeling and quantitative analysis of domains to enable co-design of system-on-chip specialization

In the materials and integration arm of the $1.5 billion effort, DARPA introduced the wining teams in two new programs, Foundations Required for Novel Compute (FRANC) and Three Dimensional Monolithic System-on-a-Chip (3DSoC). 3DSoC aims to gain a 50-fold power computation-time improvement and power reductions by growing multiple layers of interconnected circuitry atop a CMOS base. A group led by MIT’s Max Shulaker gained the lion’s share of the research funds ($61 million) for an ambitious project that aims to show that a monolithic 3D system using 90-nanometer manufacturing technology can match the performance of a CMOS chip made with today’s most advanced process technology.

PrincipalFunds (millions of US$)InstitutionsDescription
Max Shulaker61MIT, Skywater, Stanford University, CarbonicsRefined RRAM and CNFET processes for commercial fabrication of an integrated, monlithic 3D SoC
Sung Kyu Lim3.1Georgia Tech, Duke UniversityOptimized EDA software for complex, high-performance monlithic 3D SoC

FRANC is focused on using new nonvolatile memory devices to perform processing in memory. Naresh Shanbhag from the University of Illinois is leading the biggest project in that category, exploring in-memory processing with embedded MRAM. But others will look at more exotic types of memory. “FRANC seeks to utilize new materials and devices to make 10x advances in embedded, non-volatile memories with the speed of static random access memory (SRAM) and the density of storage-class memory,” said Y.K. Chen, the program manager leading FRANC, in a press release. “These advances could allow emerging memory-centric computing architectures to overcome the memory bottleneck presented in current von Neumann computing.”

PrincipalFunds (millions of US$)InstitutionsDescription
Naresh Shanbhag8.3University of Illinois Urbana-ChampaignEnergy-efficient in-memory computing with non-volatile memory
David Thompson6.7Applied mateials, ARM, Symetrix, University of Colorado, University of British ColumbiaNew correlated electronic multi-level memory devices with robust Mott transition
Wei Yi3.4HRL LaboratoriesNew active and passive memristor devices for neuromorphic functios and computation
Noah Sturcken3.1FerricIntegrated magnetic devices for efficient power devices
Sudhakar Pamarti1.9UCLAEnergy-efficient spintronics-based stochastic computing system with non-volatile magnetic memory
Jian-Ping Wang0.8University of Minnesota, University of ArizonaHigh-density magnetic memory devices with synthetic antiferromagnetic free layers for fast switching speed with low voltage and energy
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