RF Bridges to the Network
Chips that dwell at the boundary between the electronics and the transmission medium and run at network speeds are growing in importance, and so are the tools to design them
ILLUSTRATION: ARMAND VENEZIANO
This is part of IEEE Spectrum's special report: Always On: Living in a Networked World.
With the dawn of the "always connected" era, ICs for communications have grabbed the wheel from computer chips as drivers of semiconductor industry developments. The transition is more than nominal--it brings to the design procedure a new set of IC materials, processes, performance criteria, and design technologies that have remained unimportant in the digital domain.
The differences are particularly acute for circuits at the interface between the electronics and the antenna, in the case of wireless, and between the electronics and the fiber for optical networks, where ICs must run at network frequencies. Today, that means 800 MHz to 2.4 GHz for wireless networks and up to 40 GHz for optical networks. And networks are getting faster: in the wireless regime, the 5.6-GHz band is already being explored and 80-Gb/s optical networks are just around the corner.
The acknowledged market leader in design tools for RF ICs is Agilent EEsof EDA, a division of Agilent Technologies Inc., Palo Alto, Calif. But the boom in communications applications for this class of devices is luring others into the area as well. For one, Applied Wave Research Inc., El Segundo, Calif., is itching to gain a lap or two on Agilent. "We are trying to leapfrog them by providing technology that is more modern and better integrated," said the company's chief executive officer, Ted Miracco.
IBM Corp. has a different reason for being interested in the RF IC design tools. Its silicon germanium process for RF circuits is a roaring success, and customers building ICs at its foundry need tools to design them with.
The first critical job is to define the system architecture, Riccardo Giacometti, product manager for RF IC design solutions at Agilent EEsof EDA, told IEEE Spectrum. In the wireless arena, in particular, new standards are being developed at lightning speed.
Design challenges abound
System designers have precious little time to evaluate the various architectural choices--how the digital, analog, and RF portions of the system are partitioned, say, or whether to include intermediate frequencies or go directly from RF to baseband--and still get their product to market before the competition.
Selection of an architecture is based on design tradeoffs. They are made at the so-called behavioral level, before any circuits are designed. "The bottom line is that the system designer has a great deal of freedom in designing an architecture, and the best way to zero in on the best architecture is to do a lot of tradeoff analysis," said Giacometti.
To get a good measure at the behavioral level of how a system will perform, the designer must also take RF effects into account. The task includes modeling the propagation path and the effect of circuit nonlinearities on the signal as well as calculating the bit-error rate. In this process, the accuracy of the library of behavioral models for RF, analog, and digital signal processors is critical. "Our ADS system-level simulator is widely used by RF IC designers for behavioral-level analysis," said Giacometti. "It contains many component models that take RF effects into account. And it has libraries for the most important wireless communications standards."
"The onus is on the foundry's modeling group to provide designers with good models"
Early in the architectural definition process is the time to choose the materials to build the RF ICs [see interview with Richard Baldey]. There are several options. Gallium arsenide has been the material of choice for high-frequency circuits. But indium phosphide and silicon germanium are proving worthy contenders in the RF regime. Even silicon CMOS, which until recently was considered too slow, is now being used in wireless local-area networks running at 2.4 Gb/s.
Once the architecture and process are chosen, RF designers begin to craft the individual components--amplifiers, mixers, transmitters, and receivers, for example. It is crucial to have accurate device models from the foundry. "The onus is on the foundry's modeling group to provide designers with good models," said Giacometti. If the models are inaccurate, the prototypes that come back from the foundry will not meet the designers' specifications "...and not because the design is bad, but because the models do not reflect the RF performance of the devices built in the foundry's process."
The analog legacy
Two RF IC design techniques are holdovers from analog design methods: time-domain simulation, typically Spice, and schematic-based design. But as carrier frequencies rise, Giacometti sees a need for a different approach. "In the time domain, when you simulate a circuit that operates with a high-frequency carrier and a low modulation frequency, you have to simulate at the higher frequency," he said.
For example, the carrier frequency of the global system for mobile communication (GSM) is 900 MHz, four orders of magnitude higher than the 30-kHz bandwidth of the GSM signal. So the time-domain simulator spends most of its time simulating the carrier and not the signal.
In short, simulations that take days with time-domain tools can be done in minutes in the frequency domain. And shorter simulation times mean that designers can run more simulations and spend more time optimizing their designs.
The schematic-based design of RF ICs ignores the RF properties of the interconnects until the design is completely placed and routed. It may also be on the way out (just as in the digital domain).
Far more effective in the frequency regime of 5 GHz and beyond is a layout-driven approach, in which interconnects are considered from the get-go. For this approach, Microwave Office 2000, a design suite for microwave, millimeter-wave, and RF circuits developed by Applied Wave Research, may be just the ticket.
With the company's tool suite "you can tune a circuit from the layout. You can physically move lines and see in real time how the simulation results change," explained Miracco. There is no need to back-annotate or run design synchronization software, because all the data is in one database. "The schematic and the layout are basically two views of the same data," he noted.
In developing its tool suite, Applied Wave Research engineers started from a clean slate and wrote every line of code. "Every piece of the puzzle works off a common database," Miracco told Spectrum. "So it's easy to mix and match different simulation technologies, and get results efficiently."
Big Blue's designs on RF
IBM's approach to addressing the issues of communications-system design was to establish the Communications Research and Development Center (CRDC), a distributed center that links people and facilities around the world. "It brings together people that create the devices, design the circuits, and design the systems," explained IBM research staff member Sudhir Gowda, communication IC design manager, IBM Research.
IBM researchers affiliated with the center are aiming to enhance design quality and productivity by developing selected tools to complement the overall design system. "A solid simulation environment is essential for circuit analysis and optimization," explained John Darringer, system-level design manager, also at IBM Research. Accordingly, the researchers are developing accurate modeling and simulation tools to form the foundation of the system.
In development at present is a tool that can model so-called substrate coupling--the coupling of noise through the substrate. According to IBM Research staff member David Ling, designers are in need of accurate ways to predict substrate noise when the design is done and all the details are in place. "It is a complex problem because you have to analyze the whole chip," explained IBM's manager of circuit analysis, Khalid Rahmat. "You have to extract the resistive and capacitive elements of the substrate and put them in a compact form that can be simulated in a reasonable amount of time."
Other important problems in RF and analog computer-aided design, according to Ling: RF phase-noise analysis, generation of test vectors for analog circuits, and full-wave analysis of on-chip interconnect at high frequencies. "The electromagnetic nature of the interconnect at digital circuit speeds may not be important, but it becomes important at speeds of 50 or 100 GHz," he added.
IBM may be gearing up for the time when very large-scale integration of RF circuits with digital ICs becomes practical. The deed is doable with silicon germanium technology because the silicon germanium process differs only slightly from the conventional bipolar process. Moreover, with the availability of biCMOS fabrication techniques, it is not too difficult to imagine RF, analog, bipolar, and CMOS circuits all rolled into one highly integrated IC.
In fact, IBM is seeing volume production of silicon germanium chips for communications containing hundreds of analog circuits integrated with up to 400 000 digital gates, according to Darringer. "Combining high-frequency RF and high-performance digital circuitry in a single SiGe chip creates a challenging environment for design automation tool developers," he said.