ISSCC 2011: Meeting the Chip Champs

In January, IEEE Spectrum gave readers a sneak peek at some of the chip greats that would grace the International Solid-State Circuits Conference (ISSCC). This week it's time to meet them.

I must admit that I am an ISSCC newbie, and that yesterday afternoon during the "Enterprise Processors and Components" session, I found my tired self at one late presentation pencil down, counting the number of times the presenter said "leakage" instead noting all of the details of amazing chip architecture advances. But, during my more lucid moments, here's what I learned:

The program started with a talk on the speed demon, IBM's zEnterprise 196 system. It's a 512 square millimeter, 5.2 GHz chip (first commercial chip faster than 5GHz) built in IBM's 45nm SOI CMOS process. Jim Warnock, the IBM engineer who presented, said that the new design, which requires 13 levels of copper interconnect, improved efficiency by 25 percent and that resulted in an 8 to 10 percent increase in frequency.

The IBM system also benefited from out-of-order instructions processing--a technique addressed in more detail in a later paper presented by AMD's Michael Golden. After another AMD engineer Hugh McIntyre described the workings of AMD's 2-core "Bulldozer" module (in an 8-core CPU) which is built in a 32 nm SOI CMOS process, operates at 3.5 GHz in 30.9 square mm, and should also win the best name award, Golden took the audience on a tour through the CPU's out-of-order scheduler and integer unit, which increases efficiency by chewing through the data that's easiest to get at first, not necessarily what's called for first by a program. All the while, the Bulldozer saves power by avoiding dynamic logic.

That prescription for power saving was also made in Weiwu Hu's presentation on the Chinese Academy of Science's 8-core Godson-3B, which was touted as the most energy efficient of the lot. For me, it was hard to compare it to the others, given that the 299.8 squared mm chip is built using an older, 65nm CMOS process and operates at 1.05 GHz. But more knowledgable neighbors sitting nearby seemed impressed with its 3.2GFlops/Watt (peak performance 128/256GFlops for double/single precision with 40W power consumption). Hu, who is the lead architect on the project, started with some background on the chip, noting that it was part of a 2006-2020 Chinese initiative including 16 major projects such as large aircraft and high-resolution, earth-observing satellites. Hu has said that the next petascale Chinese supercomputer, the Dawning 6000, will use a Godson chip.

In the final presentation, Intel engineer Reid Riedlinger described the transistor count record-breaker--the latest in Intel's Itanium line, code named Poulson, with 3.1 billion transistors in an 18.2 mm by 29.9 mm, a 50 percent increase in transistor population over the previous processor in the line. The design has 8 cores, connected by a merry-go-round of interconnects--"a ring based system interface." Riedlinger highlighted the chip's efficiency stats, displaying a chart that showed the Poulson's increase in power management prowess over not only the previous chip line, but also a hypothetical version of its predecessor if scaled to Poulson's 32 nm CMOS process. That seemed to speak to his claims that this chip required a "complete redesign," not just a shrinking. He noted that it was a “rather exciting project in that sense.”

Related Stories

Tech Talk

IEEE Spectrum’s general technology blog, featuring news, analysis, and opinions about engineering, consumer electronics, and technology and society, from the editorial staff and freelance contributors.

Newsletter Sign Up

Sign up for the Tech Alert newsletter and receive ground-breaking technology and science news from IEEE Spectrum every Thursday.

Advertisement
Advertisement