Solid-State Circuits, in 3-D!

At this year's IEEE ISSCC, some 3-D integration technologies are ready to wear, while others will remain haute couture

9 February 2009—Chipmakers are officially headed into the third dimension, as demonstrated at this week’s IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco. For a number of years, researchers have been looking for ways to stack chips vertically to reduce communication delays through lengthy wiring. ”Three-D is an important topic this year,” says Infineon’s Werner Weber, a member of the ISSCC technology directions subcommittee. Of course, there has been activity in 3-D for at least the past two years. But what’s different this year is the presentation of a chip that’s actually on the market.

Chip firms this week are reporting progress in 3-D integration for all types of memory—dynamic random-access memory (DRAM), static random-access memory (SRAM), and NAND flash—as well as in image sensors and wireless pressure sensors. The star of the 3-D integration show, however, is Toshiba Corp., according to Weber, because its chip-scale camera module is already available.

Three-dimensional integration became a necessary solution when microprocessors became faster than memory. Consequently, the new limit on microprocessor speed was no longer the speed at which its transistors could switch on and off but the long wait to retrieve instructions and data from memory. The industry became aware of the problem about 15 years ago, but in the past five years, memory-access time lags have been increasing with each generation of chips. The problem is commonly referred to as the memory wall.

Ideally, 3-D chip stacking solves the memory-wall problem by drastically decreasing the time it takes for the signal to make it through the wiring. Instead of relying on standard interconnects, which can require a signal to traverse many meters of slender wiring, 3-D chip stacks instead rely on short, comparatively fat vertical interconnects called through-silicon vias (TSVs). These interconnects essentially punch vertically through a stack of chips to create a dense, high-speed, high-bandwidth interchip connection. That means substantial power reduction (a short line always needs less driving power than a long line), smaller systems, and faster communication.

Though 3-D integration has been a buzzword for 10 years, until now it has referred to discrete stacks of chips soldered together atop each other and connected by standard input/output wiring. This year’s chips are all stacked with TSVs.

Infineon’s tire-pressure monitor—a tire-mounted wireless node that senses pressure, inertia, and temperature—is a 3-D vertical chip stack that’s compact and robust enough to survive the rough conditions inside a tire. The stack contains a microelectromechanical sensor, a power-supply module, a microcontroller, and a transceiver. Only the transceiver and the tire-pressure sensor have TSV connections. In addition to sensing pressure, the device can also be used to monitor road conditions, tire wear, and vehicle load.

Weber, who is also a senior researcher with Infineon, says that the sensor is intended to be the second generation of a product whose first generation already populates all new U.S. cars. That device, however, has no 3-D stacking. ”The second generation still has a lot of question marks, both technological and architectural,” he says. He anticipates that the device presented at ISSCC ”will need much more basic research before it becomes a product.”

Flash-based storage is starting to replace hard-disk drives in many systems, but it will need integrated 3-D stacks to compete in some systems. The University of Tokyo and Toshiba jointly presented a 3-D integrated solid-state drive (SSD) that addresses what they called the key design issue for SSD development: decreasing power consumption. The solution was a stack of NAND flash chips, DRAM, a NAND controller, and a new low-power voltage generator. In this application, the 3-D integration lowers power consumption, because of its a short interconnects.

Toshiba wins the race to market with its 3-D stacked ”vision chip,” the first mass-produced chip using TSV technology. Stacking several components reduces the device’s overall footprint by 36 percent, to 4 by 4 by 2.5 millimeters. The chip is intended for mobile handsets, where a substantial size reduction should appeal to many buyers. Normally, image sensor chips are mounted on a multilayered printed circuit board and wired to other components, but the Toshiba 3-D implementation saves a circuit board layer, one of many improvements that, according to Toshiba engineers, reduce the cost of the camera chip by 25 percent.

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