Integrated circuits fabricated in aggressively scaled nanometer scale technologies are susceptible to a wide range of random manufacturing defects, some of which can be extremely difficult to reliably detect in post-manufacturing testing. Meanwhile commercial applications continue to demand ever-higher IC quality, most notably a “zero defect” target from automotive manufacturers. To cost-effectively meet these new quality and reliability challenges, innovative new statistical screening techniques and adaptive test methodologies are being developed. These attempt to improve test effectiveness and optimize test costs by identifying “suspect” parts for more extensive testing, using tests specially targeted at the suspected failure mode. Adaptive test methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. We present test methodologies that span both these categories, and illustrate their effectiveness with results from recently published experimental studies on automotive parts.
Adit D. Singh, Auburn University
Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, USA. Before joining Auburn in 1991, he served on the faculties at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has published over two hundred and fifty research papers, served as a consultant to several semiconductor companies, and holds international patents that have been licensed to industry.
Dr. Singh is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society. He has had leadership roles as General Chair/Co-Chair/Program Chair in dozens of international VLSI design and test conferences, and on the editorial boards of several journals. He served two elected terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and on the Board of Governors (2011-15) of the IEEE Council on Design Automation (CEDA). He received his B.Tech from the Indian Institute of Technology Kanpur, and the M.S. and Ph.D. from Virginia Tech, all in Electrical Engineering.