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Wafer-scale Nanotube Film Is Finally Here

Wafer-scale production technique could lead to single-walled carbon nanotubes finally fulfilling their promise in a range of applications

2 min read
Wafer-scale Nanotube Film Is Finally Here
An example of how the single-walled carbon nanotube film can be easily patterned using conventional photolithography techniques.
Image: Rice University/Nature Nanotechnology

Single-walled carbon nanotubes (SWCNTs) used to be the darling of those who were looking for an alternative to silicon in digital electronics. The first SWCNT-based transistors were fashioned almost twenty years ago, but scaling up the use of SWCNTs since then to very large scale integration (VLSI) processes has remained elusive.

There were two persistent problems with SWCNTs that led to much of the research community pursuing graphene instead of SWCNTs as the next great post-silicon hope: an inconsistency between semiconducting and metallic nanotubes and the frustration of trying to get all of the nanotubes to align on a wafer.

Now researchers at Rice University claim that they have struck upon a method that produces a uniform and wafer-scale film of highly aligned and densely packed SWCNTs that may finally deliver on the long-promised potential of SWCNTs.

In research published in the journal Nature Nanotechnology, the Rice researchers’ method starts by preparing a well-dispersed CNT suspension, which requires getting just the right concentration of CNT powder with a surfactant in water. The next step involves a vacuum filtration method that has long been the established technique for creating wafer-scale films of CNTs with controllable thickness. The CNT suspension is poured into a filtration funnel with small pores. Pressure pushes the suspension through those pores so that CNTs are left behind on the filter membrane.

The SWCNTs spontaneously align as long as both the surfactant level in the dispersion and the CNT concentration are just right and the filtration process is done slowly and carefully. When these criteria are met, a wafer-scale, uniform and aligned SWCNT film forms on the filter membrane.

The film can be easily transferred onto a substrate by dissolving the filter membrane on the substrate, which leaves perfectly aligned SWCNTs in place. In addition to the problem of alignment, many methods that have been used for aligning SWCNTs result in low density. However, in this method the density is quite high with 1×106 CNTs found in a cross-sectional area of 1 square micrometer. Finally, the film can be patterned by standard photolithography methods.

The researchers have put the resulting material to the test by producing terahertz/infrared polarizers using a mix of metallic and semiconductor CNTs; and they fabricated thin-film transistors, polarized light-emission devices and polarization-sensitive photodetectors using only semiconducting CNTs.

The Rice team believes that this method should create not only new avenues for fundamental research in physics, chemistry and materials science, but will also enable the use of SWCNTs in electronics, optoelectronics, sensing, imaging and medicine.

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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