Can Two-dimensional Semiconductors Created Using Liquid Metals Forestall Moore’s Law's Demise?

With the potential to further shrink transistors and improve performance, these ultra-thin semiconducting materials could also make flexible electronics a practical reality

3 min read
Researcher Yifang Wang is holding a silicon substrate on which a monolayer of MoS2 has been transferred.
Researcher Yifang Wang is holding a silicon substrate on which a monolayer of MoS2 has been transferred.
Photo: Jialuo Han

As the semiconductor industry witnesses the winding down of the expectation that the number of transistors that can be shoehorned into silicon microchips will double every couple of years, researchers are coming up with new ways to keep the effect of Moore’s Law rolling along. One such method with exciting prospects employs liquid metals to produce two-dimensional semiconducting materials with atomic-scale thickness. This enables the creation of a transistor channel between source and drain that is almost an order of magnitude thinner than those employed in silicon transistors. In addition, they possess intriguing properties such as a variety of band gaps and carrier concentrations, as well as unique transducing properties.

“The two-dimensional confinement of free charge-carriers—namely electrons and holes—in these materials provides a pathway to move along with reduced charge scattering,” says Kourosh Kalantar-Zadeh, a professor of engineering at the University of New South Wales, Australia. “This means extremely small resistance. In theory, they can also switch very fast and switch off to absolute zero resistance during non-operational states due to their very thin nature.”

But several barriers make it difficult to use these new materials as ultra-thin semiconductors for integrated circuits. Besides imperfections and defects arising in their production that can inhibit electron flow, a major issue to date has been the grain barriers that exist across their planes when they’re produced using conventional deposition methods.

To overcome this problem, Kalantar-Zadeh’s research group has developed a new deposition method to produce one of the most promising ultra-thin semiconductor materials, molybdenum disulfide (MoS2), without grain barriers.

“We use the unique capability of gallium metal, which, unlike mercury for instance, is much less hazardous and has the amazing quality of turning to liquid at just 29.8 0C,” says Yifang Wang, a member of Kalantar-Zadeh’s group and first author of a paper published on the research in Advanced Functional Materials this October. “Indeed, it turns to liquid when held in the palm of your hand.”

And because gallium is a melted metal, she says its surface is atomically smooth, yet like conventional metals, its surface provides a large number of free electrons to facilitate chemical reactions, which is important for the new method of deposition.

Kalantar-Zadeh explains the method as follows. The sources of molybdenum and sulfur are brought near to the surface of the liquid gallium. This causes a chemical reaction that forms molybdenum sulfur bonds that in turn create MoS2. The newly formed material is grown on the atomically smooth surface of the gallium like a skin, so it is naturally formed and grain free. This process takes place in an aqueous solution and requires annealing to remove hydration. Distance-dependent surface forces such as electrostatic or dipolar forces are then used to remove the semiconductor skin from the gallium liquid and to transfer it to a substrate ready for turning into transistor elements. Such forces do not exist on the surface of liquid metals, and so the synthesized MoS2 does not adhere to their surfaces.

Illustration of the 2D semiconductor process Illustration: Mohannad Mayyas

“Unlike conventional chips that require a silicon substrate, the molybdenum disulfide skin can be deposited onto almost anything non-metallic: glass, a polymer,” says Kalantar-Zadeh. “You can roll it out or print it out anywhere you like. If you want something flexible, if you want to bend it, for instance, you can deposit it on a suitable polymer substrate to produce flexible electronics.”

And because the material is thinner than silicon, a number of layers can be added as desired, while standard chip packaging can also be used.

Having demonstrated the deposition method’s feasibility, the researchers are now working to streamline it so that it can be transferred from the lab to commercial fabs—something Kalantar-Zadeh estimates can be accomplished in the next several years. 

The researchers are also planning to extend the method to create other two-dimensional semiconducting, dielectric, and conducting materials such as gallium arsenide, gallium sulfide, and indium tin oxide. 

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
DarkBlue1

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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