Tunable Logic

New logic family could help optimize FPGA performance and power

3 min read

5 October 2009—As engineers shrink transistors to tinier dimensions, they're finding it harder and harder to keep the devices from leaking current and wasting power, even when they're switched off. Stanford University researchers, led by electrical engineering professor and Rambus cofounder Mark Horowitz, think they've found a way to effectively plug the leaks, at least for certain types of chips. They've invented a new family of logic circuits that let designers tune a transistor characteristic critical to balancing power loss and performance, even after the chips have been constructed.

"There's always a choice between power consumption and performance when you do a [circuit] design," says Rajit Manohar, a professor in Cornell University's school of electrical and computer engineering, who was not involved in the work. The Stanford technique, called pseudostatic logic, allows you to "pick your trade-off between power and performance" after the chip arrives at your door, he says.

When incorporated into a critical part of a reconfigurable IC, the design gave researchers the ability to tune the chip's performance and energy demands over a much wider range than current conventional techniques allow.

Most microprocessors can dial up performance at the expense of power consumption, or vice versa, by simply increasing or decreasing the supply voltage. Tricks like that, for the most part, only diminish dynamic power, which is lost when transistors switch. But as chips get smaller, dynamic power isn't the only factor affecting chip performance. Static power, lost by leaking current while transistors are off, sucks up valuable energy.

Leakage can be controlled by tricks that change the transistor's threshold voltage, below which the transistor is turned off. But these tricks have become less effective as transistors scale down, Manohar says. "A new knob is needed" that will control this leakage variable, says Bita Nezamfar, who worked on the new logic family while she was a graduate student at Stanford.

The Stanford researchers claim that pseudostatic logic, which they described in a recent issue of IEEE Journal of Solid State Circuits, could do the job better. The new logic yields the same effect as that of tweaking a transistor's threshold voltage, but it works by changing the voltage between the gate and source, which can be tuned over a wider range.

With pseudostatic logic, the supply voltage driving every other gate in a logic block is shifted, or skewed, by a certain amount. That means that when the transistor is off, the voltage between the transistor's gate and source isn't zero but rather some positive or negative value. A positive skew boosts performance, making transistors faster, while a negative skew reduces leakage.

Horowitz and his colleagues say that this type of logic is particularly useful for field-programmable gate arrays (FPGAs), which are made of blocks of programmable logic and interconnect circuits and must serve applications with a wide variety of power and performance demands. The Stanford team substituted pseudostatic logic in the interconnect circuits of a test FPGA and were able to reduce power consumption by 35 percent without sacrificing performance. Or, they could choose to boost performance by 20 percent without eating up more power. However, their logic does require two extra voltage supplies to do the skew, which could put off companies whose designs can't accommodate the cost of added components and complexity.

Horowitz says his team is talking to the FPGA community about their logic, and that some companies he won't name have shown an interest in exploring its use.

Manohar, who cofounded the FPGA firm Achronix, says that incorporating the technology may not depend on whether it's a good idea or not. "Business realities don't always align with the best technology," he says. "There are a lot of options available to [industry] to improve their system," and they have to choose what to spend time on. And companies may prefer to stick with the designs they're used to. A spokesperson from FPGA firm Altera says that a leakage-reducing technique in use today, called body bias, should still work for future chips.

This article is for IEEE members only. Join IEEE to access our full archive.

Join the world’s largest professional organization devoted to engineering and applied sciences and get access to all of Spectrum’s articles, podcasts, and special reports. Learn more →

If you're already an IEEE member, please sign in to continue reading.

Membership includes:

  • Get unlimited access to IEEE Spectrum content
  • Follow your favorite topics to create a personalized feed of IEEE Spectrum content
  • Save Spectrum articles to read later
  • Network with other technology professionals
  • Establish a professional profile
  • Create a group to share and collaborate on projects
  • Discover IEEE events and activities
  • Join and participate in discussions