The Incredible Shrinking Chip Industry

The field has narrowed considerably, especially when it comes to making advanced chips, GlobalFoundries CEO says

2 min read
The Incredible Shrinking Chip Industry

Discussions of the future of chipmaking—particularly at a fundamental device conference like the IEEE International Electron Devices Meeting (IEDM)—tend to focus on engineering challenges. How small can we make this transistor? How fast will it switch? How much energy will it leak when it’s off? 

But even here the economic side of the equation can’t be ignored: after all, the best transistors won’t do the world any good if they’re too expensive to make. On Tuesday at IEDM, GlobalFoundries CEO Ajit Manocha drove home some of the issues that make the future of the chip industry more than a little murky.

By Manocha’s count, TSMC, GlobalFoundries, Intel, and Samsung are the only companies left pursuing the manufacturing technology needed to make the most advanced chips. Two of those companies (TSMC and GlobalFoundries) are foundries, which offer their chipmaking services to other firms. Manocha categorizes the other two, Intel and Samsung, as integrated device manufacturers (IDM’s), manufacturing their own designs, although Samsung, and to a lesser extent, Intel, also make chips for others.

This chipmaking complement is notable because it’s quite small. Once upon a time (about 12 years ago), Manocha said, there were a good 20 companies making advanced chips. Now “the list has shrunk…to four.”

This consolidation is driven primarily by cost. R&D is getting more and more expensive. And the cost of building a new fabrication plant is getting exceedingly steep: GlobalFoundries, for example, expects to spend about US $6.9 billion on the company’s new fab in upstate New York.

There are more challenges to come. Last week, outgoing Intel CEO Paul Otellini noted two significant hurdles coming up. One is the transition to 450-mm wafers from 300-mm wafers, a move that could drive the cost of new chip fabs to an even more staggering $10 billion. Then there is the transition to extreme ultraviolet lithography, which may one day save a lot of steps in patterning chips but will also add to the expense.

According to a transcript posted to the website Seeking Alpha, Otellini described those upcoming hurdles as a “chasm” that not every company may be able to cross. “I think you will likely see the structure of the industry evolve pretty dramatically over the next 4 to 5 years.”

The foundries, not unexpectedly, don’t look very healthy in Otellini’s crystal ball. Intel, which leads the field in R&D spending, has traditionally been the first with new transistor technologies like new gate stack materials and, more recently, 3-D transistors. In the past, Otellini said, other companies could follow suit by reverse engineering what Intel has done. Now, “you get to the dimensions that we are at today, and reverse engineering destroys the part in a way that you can't analyze's becoming more difficult for everybody to, sort of, ride the coattails.”

To stay in an increasingly fast-moving game, Manocha envisions foundries will have to evolve into “virtual IDM’s” collaborating very early and very closely with customers and other companies that are part of the chipmaking ecosystem. As chip design and the underlying devices get more complex, it seems like that level of collaboration will be vital. 

But will it be enough to keep the foundries competitive? Could their business model eventually displace vertically integrated ones like Intel's? These are oldquestions. But given the extreme consolidation of the field and the quickening pace of manufacturing process development, they’re taking on a new level of urgency.

(Image: Intel)



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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

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A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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