Continuing to scale down the size of transistor features has become costlier and trickier in recent years. So much so that only four manufacturers of logic chips—GlobalFoundries, Intel, Samsung, and TSMC—were even planning to continue the multibillion-dollar effort. Those ranks have now thinned, and schedules for the remaining companies are slipping. But don’t count Moore’s Law out quite yet. If you’ve got the cash, you can now hold evidence of its power in your hand in the form of at least two smartphones. And new ways to improve performance without shrinking transistors appear to be in the offing.
In August, GlobalFoundries announced a halt to its development of bleeding-edge chipmaking processes. It had planned to move to the 7-nanometer node and then begin to use extreme-ultraviolet lithography (EUV) to make that process cheaper. From there, it would have developed even more advanced lithography that would allow for 5- and 3-nm nodes. Despite having installed two EUV machines at its Fab 8 facility in Malta, N.Y., all those plans are now on indefinite hold, and the company may even sell the EUV systems back to their manufacturer, ASML Holding.
“We all stared at the numbers, and it was pretty clear that for the bleeding-edge stuff, the [return on investment] is continuing to erode,” says Gary Patton, GlobalFoundries’ chief technical officer. In the end, company executives chose profitability.
GlobalFoundries isn’t the only company struggling with new processes. Intel revealed earlier this year that it was delaying its move to a 10-nm process until 2019. (Intel’s 10-nm process is thought to be roughly equivalent to other companies’ 7-nm processes.) That puts a yawning five-year gap between manufacturing nodes for the company.
But the move to 7 nm has clearly gone pretty well for Taiwan Semiconductor Manufacturing Co. At an event in September, Apple executives said that the new iPhone Xs and Xs Max will be the first smartphones with processors made using 7-nm manufacturing technology. A few weeks earlier, Huawei Technologies Co. introduced its own 7-nm smartphone processor, which was set to debut in a phone a couple of weeks after those iPhones went on sale. TSMC is the real winner here; it makes both companies’ chips.
TSMC went into volume production with 7-nm tech in April and is bullish about its plan to go further. “Scaling will continue to 3 nm and 2 nm,” TSMC chairman Mark Liu told attendees of Semicon Taiwan in September. Meanwhile, rival Samsung is moving toward commercial 7-nm production later this year or in early 2019.
Seven nanometers is hardly where all the action is, of course. Fabs that are further from the edge are expanding, and new ones are under construction. According to the World Fab Forecast Report, from the industry association SEMI, spending on chipmaking equipment will grow 14 percent in 2018 to US $62.8 billion, and investment in new fab construction is set to hit $17 billion, capping four years of growth.
But who needs scaling, really? There are ways to get better performance besides struggling up the Moore’s Law ladder.
A $61 million project under DARPA’s Electronics Resurgence Initiative plans to produce chips made on decades-old fabrication processes that are competitive with 7-nm technologies by using monolithic 3D integration. The project is centered at the SkyWater Technology Foundry, a 90-nm silicon plant in Bloomington, Minn. The technology is based on a process that allows carbon nanotube transistors and resistive RAM memory to be built on top of ordinary CMOS logic chips. “If it all works as planned, it’s like setting the bar back at 90 nm, and we can continue to scale,” says Tom Sonderman, SkyWater’s president.
Another solution is emerging from Silicon Valley–based Atomera. The company has developed a technique that boosts the speed of transistors, lessens variability between devices on the same chip, and improves the reliability of those devices by keeping them in a youthful state. It involves burying atom-thin layers of oxygen just below the surface of a transistor’s silicon. Atomera expects that this method, called Mears Silicon Technology (MST), will give chip designers an opportunity to improve their systems without the expense required to shrink transistors. “It can be used across all different process nodes—from legacy analog to those still in development now,” says Scott Bibaud, the company’s president and CEO.
This article appears in the November 2018 print issue as “3 Directions for Moore’s Law.”