The Art of Failure 2010

The beauty-and creepiness-of chip defects

1 min read

Image: Ng Lay Sim
What analysts visualize during failure analysis sometimes has more to do with the chores on their to-do lists than the task at hand. This submission shows a silicon sample being thinned for transmission electron microscopy. The area on the right side of the image cut more slowly than the rest of the layer, resulting in a clothespin-like shape that reminded the analyst to do his laundry. <

Just as one man’s trash is another man’s treasure, one person’s systems failure is another one’s masterpiece. This is the third year that the “Art of Failure Analysis”was featured at the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). Participants submitted the most intriguing images they’d captured during chip autopsies. Favorite pictures from the collection, which range from charming to just plain creepy, were on display at the symposium from 5 to 9 July in Singapore.

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