The Art of Failure 2010

The beauty-and creepiness-of chip defects

1 min read

Image: Rahmat Agung Susantyoko
This year’s first-prize winner in the “Art of Failure Analysis” contest is an image of a bed of 0.13-micrometer-wide “nanoflowers” sitting on a silicon substrate. The flowers “blossomed” when an array of vertically oriented silicon nanowires bent from their original upright position. Rahmat Agung Susantyoko, who took the image, was given the task of monitoring the height of arrays of silicon nanowires. Nanowires of a certain height bent together to form the flowers.

Just as one man’s trash is another man’s treasure, one person’s systems failure is another one’s masterpiece. This is the third year that the “Art of Failure Analysis”was featured at the IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). Participants submitted the most intriguing images they’d captured during chip autopsies. Favorite pictures from the collection, which range from charming to just plain creepy, were on display at the symposium from 5 to 9 July in Singapore.

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper
Green

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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