Intel Drives New Bus for Future Chiplets

At DARPA’s Electronics Resurgence Initiative Summit, speaker after speaker agreed that the chiplets are coming. Instead of building complex systems-on-chip as one piece of silicon, as is done today, future systems will be made of smaller, cheaper, independently designed component chips bound together on a larger slice of silicon by high-bandwidth interconnects. One of the greatest challenges researchers face is getting these chiplets to communicate properly and do so at a speed and energy cost that’s close to what they’d be if the system were all one piece of silicon.

Intel CTO Mike Mayberry unveiled his company’s contribution toward that effort on 24 July; Mayberry says that Intel will provide its Advanced Interface Bus (AIB) royalty-free to help link chiplets together. AIB is a standard communications interface made for connecting different dies (unpackaged chips) in the same package.

Intel already uses AIB in so-called 2.5-D packages, Intel senior principal engineer Sergey Shumarayev told engineers at the event. These packages integrate multiple chips on top of a silicon interposer chip, which is then packaged up. The company’s Stratix 10 FPGA is one example.

Andreas Olofsson, manager for DARPA’s CHIPS program, which includes chiplets research, noted the need for a standard communications interface. “First, we need a plug-and-play standard—a sort of Ethernet for chiplets,” he said. “Once we have that standard, you can imagine vendors offering a number of chiplets for sale.” Intel is pushing AIB to become that standard.

Interconnects using the standard will have to be capable of handling a lot of data without expending much energy. It will have to cost less than 1 picojoule to move a bit and be capable of moving 1 terabit per millimeter.

Other companies are also researching ways to make chiplets work. AMD unveiled a way to keep networks of chiplets from falling into a state of paralysis last month.